Beam reconstruction method, antenna, and microwave device

    公开(公告)号:US11605901B2

    公开(公告)日:2023-03-14

    申请号:US17150320

    申请日:2021-01-15

    Abstract: A beam reconstruction method includes: generating or receiving a radio frequency signal, determining a to-be-adjusted beam angle, loading a voltage bias value on each liquid crystal metasurface array unit among a plurality of liquid crystal metasurface array units in a liquid crystal metasurface array based on the beam angle, and either emitting the generated radio frequency signal transmitted through the liquid crystal metasurface array or directing the received radio frequency signal through the liquid crystal metasurface array to a feed of an antenna. A lateral offset of a feed phase center is generated based on the voltage bias value after the radio frequency signal is transmitted through the liquid crystal metasurface array.

    SIM Card Detection Failure Recovery Method for Electronic Device and Electronic Device

    公开(公告)号:US20220327036A1

    公开(公告)日:2022-10-13

    申请号:US17641029

    申请日:2020-07-22

    Abstract: A subscriber identification module (SIM) card detection failure recovery method for an electronic device includes that the electronic device identifies a card recovery scenario, where card recovery includes whether to power on a SIM card. A configurable timer is started based on the card recovery scenario. The electronic device periodically obtains, based on a time set by the timer, power-on information for powering on the SIM card. The electronic device determines a power-on condition of the SIM card based on the power-on information. If the power-on condition is met, the electronic device powers on the SIM card.

    Chip and chip burning method
    33.
    发明授权

    公开(公告)号:US10901029B2

    公开(公告)日:2021-01-26

    申请号:US15812640

    申请日:2017-11-14

    Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

    Data Protection Circuit of Chip, Chip, and Electronic Device

    公开(公告)号:US20190266358A1

    公开(公告)日:2019-08-29

    申请号:US16411230

    申请日:2019-05-14

    Abstract: A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.

    Antenna and communications device
    35.
    发明授权

    公开(公告)号:US10044492B2

    公开(公告)日:2018-08-07

    申请号:US15083985

    申请日:2016-03-29

    Abstract: Embodiments of the present invention provide an antenna and a communications device, and relate to the field of wireless communications technologies. The antenna includes at least one receive antenna unit, at least one transmit antenna unit, a transmit and receive antenna unit connected to a three-port component having a circulator characteristic, a signal output port, and a signal input port, where each receive antenna unit and a receiver port of the three-port component are both connected to the signal output port by using a power combiner, and the signal output port is configured to connect to a receiver; and each transmit antenna unit and a transmitter port of the three-port component are both connected to the signal input port by using a power divider, and the signal input port is configured to connect to a transmitter.

    CLOCK FREQUENCY DETECTION METHOD AND APPARATUS

    公开(公告)号:US20180137276A1

    公开(公告)日:2018-05-17

    申请号:US15812992

    申请日:2017-11-14

    Inventor: Qi Su Jiayin Lu Yu Liu

    Abstract: Embodiments of the present disclosure disclose a clock frequency detection method and apparatus. The method includes: dividing a known internal clock frequency range of the system into n frequency intervals, where each frequency interval is corresponding to a frequency detection module, and n is an integer greater than or equal to 2; obtaining a current internal clock frequency of the system, and using the current internal clock frequency as a reference clock frequency; selecting a frequency detection module corresponding to a frequency interval according to the reference clock frequency; and detecting, by the selected frequency detection module, a to-be-detected clock according to a frequency offset range of the reference clock frequency. By using the present disclosure, a risk that an internal clock of the system is attacked may be reduced, and system security may be improved.

    Chip and Chip Burning Method
    37.
    发明申请

    公开(公告)号:US20180136274A1

    公开(公告)日:2018-05-17

    申请号:US15812640

    申请日:2017-11-14

    Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

    Interference Signal Cancellation Apparatus and Method

    公开(公告)号:US20180083659A1

    公开(公告)日:2018-03-22

    申请号:US15827388

    申请日:2017-11-30

    Inventor: Yu Liu

    CPC classification number: H04B1/10 H04B1/525 H04B1/7107 H04B15/02

    Abstract: An interference signal cancellation apparatus, includes a first power divider configured to divide a cancellation reference signal link corresponding to a transmit antenna into a first reference link and a second reference link. The apparatus includes a second power divider configured to divide a signal receiving link connected to a receive antenna into a first receiving link and a second receiving link, and use the first receiving link as an output link. The apparatus includes a primary cancellation unit that is located at the first reference link and that is connected to the signal receiving link by using a coupler. The apparatus includes a secondary cancellation unit that is located at the second reference link and that is connected to the second receiving link by using a coupler. The apparatus includes a control module connected to the second receiving link, the primary cancellation unit, and the secondary cancellation unit.

    JTAG DEBUG APPARATUS AND JTAG DEBUG METHOD
    39.
    发明申请

    公开(公告)号:US20180059184A1

    公开(公告)日:2018-03-01

    申请号:US15686740

    申请日:2017-08-25

    Abstract: The JTAG debug apparatus includes: a TAP controller, configured to communicate with outside by using an external JTAG port, and generate, based on a signal received from the JTAG port, a debug signal including an address of the to-be-debugged unit and a debug instruction, where the debug signal is a JTAG port signal based on the JTAG protocol; a signal conversion unit, configured to receive the debug signal that is output from the TAP controller, and convert the debug signal from the JTAG port signal to a bus slave port signal that can access a slave port of the to-be-debugged unit; and a bus, configured to obtain the debug signal that is converted to the bus slave port signal and that is output from the signal conversion unit, and transmit, based on the debug signal, the debug instruction to the to-be-debugged unit indicated by the address of the to-be-debugged unit.

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