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93 条记录 (耗时 0.027 秒)

    Driver/equalizer with compensation for equalization non-idealities
    31.
    发明授权
    Driver/equalizer with compensation for equalization non-idealities 失效
    驱动器/均衡器补偿均衡非理想

    公开(公告)号：US07411422B2

    公开(公告)日：2008-08-12

    申请号：US11103789

    申请日：2005-04-12

    申请人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

    发明人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H04L25/03885 ,  H04L25/0272 ,  H04L25/03343

    摘要： A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.

    摘要翻译： 高速串行数据通信系统包括用于校正均衡误差的规定，特别是由均衡器非理想性引入的错误。 在数据发射机上实现均衡，并且基于差分对的输出处的动态电流减法。 当位时间> 0时，误差电流从总驱动器电流中去除或减去，从而保持从位时间0到位时间> 0的恒定总电流。 通过使用相反性别的场效应晶体管减去位时间> 0时的电流，也可以实现相同的结果。 误差电流可以从仿真或使用驱动程序的副本通过反馈凭经验确定。 用于实现均衡纠错的电路和所得到的电网分析被显示和描述。

    Structure and method for providing gate leakage isolation locally within analog circuits
    33.
    发明授权
    Structure and method for providing gate leakage isolation locally within analog circuits 失效
    在模拟电路中局部提供栅极泄漏隔离的结构和方法

    公开(公告)号：US07268632B2

    公开(公告)日：2007-09-11

    申请号：US11163013

    申请日：2005-09-30

    申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    IPC分类号： H03L7/00 ,  H03L7/099 ,  H03B5/18

    CPC分类号： H03L7/093 ,  H03L7/0891

    摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

    摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

    Method and circuit for increased noise immunity for clocking signals in high speed digital systems
    34.
    发明授权
    Method and circuit for increased noise immunity for clocking signals in high speed digital systems 失效
    用于提高高速数字系统中时钟信号抗噪声的方法和电路

    公开(公告)号：US07034566B2

    公开(公告)日：2006-04-25

    申请号：US10777952

    申请日：2004-02-12

    申请人： Hayden C. Cranford, Jr. ,  Joseph M. Stevens

    发明人： Hayden C. Cranford, Jr. ,  Joseph M. Stevens

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0005 ,  H03K19/018585

    摘要： Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.

    摘要翻译： 描述了用于在高速数字系统中提高时钟信号的抗噪声性的方面。 这些方面包括使用用于多个负载电路的单个缓冲电路来缓冲差分时钟信号，并且配置单个缓冲器电路以适应接收差分时钟信号的负载电路的数量的变化。 配置在调整到负载电路数量的变化时，可实现时钟信号输出的恒定带宽和电压电平。

    Variable gain amplifier with reduced power consumption
    35.
    发明授权
    Variable gain amplifier with reduced power consumption 有权
    可变增益放大器，功耗降低

    公开(公告)号：US08183920B2

    公开(公告)日：2012-05-22

    申请号：US12828238

    申请日：2010-06-30

    申请人： Jieming Qi ,  David W. Boerstler ,  Minhan Chen ,  Hayden C. Cranford, Jr.

    发明人： Jieming Qi ,  David W. Boerstler ,  Minhan Chen ,  Hayden C. Cranford, Jr.

    IPC分类号： H03F3/45

    CPC分类号： H03G3/004 ,  H03F1/0205 ,  H03F3/189 ,  H03F3/45632 ,  H03F2200/294 ,  H03F2200/555 ,  H03F2203/45418

    摘要： A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

    摘要翻译： 可变增益放大器包括被配置为接收一对差分信号的第一差分信号的第一共模（CM）节点。 第一调节器耦合到第一CM节点，第一调节器被配置为生成第一CM偏移。 第二CM节点被配置为接收该对差分信号的第二差分信号。 第二调节器耦合到第二CM节点，第二调节器被配置为生成第二CM偏移。 在一个实施例中，第一CM偏移和第二CM偏移量一起包括净CM偏移，净CM偏移被配置为替换当前源净偏移。

    System and circuit for determining data signal jitter via asynchronous sampling
    36.
    发明授权
    System and circuit for determining data signal jitter via asynchronous sampling 有权
    用于通过异步采样确定数据信号抖动的系统和电路

    公开(公告)号：US07930120B2

    公开(公告)日：2011-04-19

    申请号：US12103689

    申请日：2008-04-15

    申请人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    发明人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    IPC分类号： G06F19/00 ,  H04B17/00

    CPC分类号： G01R31/31725 ,  G01R29/26 ,  G01R31/31709 ,  H04L1/205

    摘要： A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

    摘要翻译： 用于通过异步采样确定数据信号抖动的系统和电路提供了用于测量数据信号抖动的低成本和生产可集成机制。 数据信号被边缘检测并通过不相关频率的采样时钟采样，采样值根据时基上的样本的折叠而被收集在直方图中。 通过扫描确定时基以检测折叠数据的最小抖动。 正确的估计时基周期的直方图代表数据信号边缘位置的概率密度函数，抖动特性由密度函数峰的宽度和形状决定。 可以通过调整用于在整个样本集中折叠数据的时基来纠正频率漂移。

    High speed serial link output stage having self adaptation for various impairments
    38.
    发明授权
    High speed serial link output stage having self adaptation for various impairments 失效
    具有各种损伤的自适应的高速串行链路输出级

    公开(公告)号：US07769057B2

    公开(公告)日：2010-08-03

    申请号：US12175846

    申请日：2008-07-18

    申请人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

    发明人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

    IPC分类号： H04J99/00 ,  H04B3/00

    CPC分类号： H04L25/0292 ,  H04L25/03885

    摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.

    摘要翻译： 提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。

    On-chip electromigration monitoring
    39.
    发明授权
    On-chip electromigration monitoring 有权
    片上电迁移监测

    公开(公告)号：US07719302B2

    公开(公告)日：2010-05-18

    申请号：US12215732

    申请日：2008-06-30

    申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

    摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.

    摘要翻译： 提供了一种用于监测半导体芯片组件内的互连电阻的方法。半导体芯片组件可以包括具有在半导体芯片的表面处露出的触点的半导体芯片和具有与触点导电连通的露出端子的基板。 半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。 在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。 以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。 基于这种比较的结果，可以做出是否指示动作条件的决定。