公开(公告)号：US06562699B1

公开(公告)日：2003-05-13

申请号：US09202714

申请日：1998-12-21

申请人： Kotaro Kataoka ,  Hiroshi Iwata ,  Masayuki Nakano

发明人： Kotaro Kataoka ,  Hiroshi Iwata ,  Masayuki Nakano

IPC分类号： H01L21322

CPC分类号： H01L21/02043 ,  H01L21/28052 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

摘要翻译： 通过除去存在于硅层表面和其表面上的卤素原子，使得卤素原子的浓度变为100ppm或更低，并且在所得硅层上形成电极，可以制备具有低电阻的电极， 并且还可以生产高可靠性的半导体器件。

公开(公告)号：US07135386B2

公开(公告)日：2006-11-14

申请号：US10394024

申请日：2003-03-24

申请人： Kotaro Kataoka ,  Hiroshi Iwata ,  Masayuki Nakano

发明人： Kotaro Kataoka ,  Hiroshi Iwata ,  Masayuki Nakano

IPC分类号： H01L21/322

CPC分类号： H01L21/02043 ,  H01L21/28052 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

公开(公告)号：US20060197142A1

公开(公告)日：2006-09-07

申请号：US11366479

申请日：2006-03-03

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

IPC分类号： H01L29/788

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

公开(公告)号：US20050280065A1

公开(公告)日：2005-12-22

申请号：US11142770

申请日：2005-06-02

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/792

CPC分类号： H01L29/6684 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

摘要翻译： 半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的单个栅电极。 形成在栅电极两侧的第一和第二记忆功能体。 在栅极侧的基板的表面形成P型沟道区。 在沟道区域的两侧形成N型第一和第二扩散区域。 沟道区域由位于第一和第二存储器功能体之下的偏移区域和位于栅电极下方的栅极电极构成。 赋予偏移区域的P型导电性的掺杂剂的浓度有效地低于向区域下方的栅电极施加P型导电性的掺杂剂的浓度。 这使得可以提供容易缩小的半导体存储装置。

公开(公告)号：US06927463B2

公开(公告)日：2005-08-09

申请号：US10439540

申请日：2003-05-15

申请人： Hiroshi Iwata ,  Seizou Kakimoto ,  Masayuki Nakano ,  Toshimasa Matsuoka

发明人： Hiroshi Iwata ,  Seizou Kakimoto ,  Masayuki Nakano ,  Toshimasa Matsuoka

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/772 ,  H01L29/76

CPC分类号： H01L27/0928 ,  H01L21/82385 ,  H01L21/823892

摘要： A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的深阱区; 形成在深井区域中的多个第二导电类型的浅阱区; 分别形成在所述多个浅井区域中的所述第一导电类型的源极区域和漏极区域; 在所述源极区域和所述漏极区域之间形成的沟道区域; 形成在沟道区上的栅极绝缘膜; 以及形成在所述栅极绝缘膜上的栅电极，其中所述栅电极与相应的一个浅阱区电连接，并且所述浅阱区与相邻的浅阱区电分离。

公开(公告)号：US06720627B1

公开(公告)日：2004-04-13

申请号：US09698097

申请日：2000-10-30

申请人： Hiroshi Iwata ,  Masayuki Nakano ,  Shigeki Hayashida ,  Seizou Kakimoto ,  Toshimasa Matsuoka

发明人： Hiroshi Iwata ,  Masayuki Nakano ,  Shigeki Hayashida ,  Seizou Kakimoto ,  Toshimasa Matsuoka

IPC分类号： H01L31113

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823807 ,  H01L29/665

摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.

摘要翻译： 公开了一种半导体器件及其制造方法。 在硅半导体衬底上形成氮化硅膜。 然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。 硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。 制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。

公开(公告)号：US06255704B1

公开(公告)日：2001-07-03

申请号：US08881697

申请日：1997-06-24

申请人： Hiroshi Iwata ,  Seizou Kakimoto ,  Masayuki Nakano ,  Toshimasa Matsuoka

发明人： Hiroshi Iwata ,  Seizou Kakimoto ,  Masayuki Nakano ,  Toshimasa Matsuoka

IPC分类号： H01L2976

CPC分类号： H01L27/0928 ,  H01L21/82385 ,  H01L21/823892

摘要： A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的深阱区; 形成在深井区域中的多个第二导电类型的浅阱区; 分别形成在所述多个浅井区域中的所述第一导电类型的源极区域和漏极区域; 在所述源极区域和所述漏极区域之间形成的沟道区域; 形成在沟道区上的栅极绝缘膜; 以及形成在所述栅极绝缘膜上的栅电极，其中所述栅电极与相应的一个浅阱区域电连接，并且所述浅阱区域与相邻的浅阱区域电分离。

公开(公告)号：US08059080B2

公开(公告)日：2011-11-15

申请号：US11945129

申请日：2007-11-26

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

IPC分类号： G09G3/34

CPC分类号： H01L27/1203 ,  G02F1/13454 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L21/28282 ,  H01L21/84

摘要： To provide a semiconductor storage unit that has a simple structure requiring only a small number of processes to produce, and is provided with a gate insulating film having a memory function. The semiconductor storage unit has a semiconductor layer, two diffusion layer regions forming a source region and a drain region, which are formed on the semiconductor layer, a channel region fixed between the two diffusion layer regions, a gate insulating film that is formed on the channel region, and made of a silicon oxide film containing carbon atoms of 0.1 to 5.0 atomic percent, and a gate electrode formed on the gate insulating film.

摘要翻译： 提供具有仅需要少量工艺制造的简单结构的半导体存储单元，并且设置有具有记忆功能的栅极绝缘膜。 半导体存储单元具有半导体层，形成在半导体层上的源极区和漏极区的两个扩散层区域，固定在两个扩散层区域之间的沟道区域，形成在栅极绝缘膜上的栅极绝缘膜 沟道区域，由碳原子数为0.1〜5.0原子％的氧化硅膜构成，栅极形成在栅极绝缘膜上。

公开(公告)号：US07598559B2

公开(公告)日：2009-10-06

申请号：US11366479

申请日：2006-03-03

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

IPC分类号： H01L29/94

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

摘要翻译： 半导体存储装置具有半导体层，其具有通过第一导电类型区域彼此分离的第一导电类型区域和两个第二导电类型区域，形成在半导体层的表面上的存储功能体和栅极电极。 记忆功能体具有位于电荷存储绝缘体与半导体层之间的电荷存储绝缘体和电荷保持绝缘体，兼作栅极绝缘膜。 电荷保持绝缘体含有这样的杂质原子（磷），使本征半导体成为第二导电类型。

公开(公告)号：US20080136757A1

公开(公告)日：2008-06-12

申请号：US11945129

申请日：2007-11-26

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

IPC分类号： G09G3/36 ,  H01L29/792

CPC分类号： H01L27/1203 ,  G02F1/13454 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L21/28282 ,  H01L21/84

摘要： To provide a semiconductor storage unit that has a simple structure requiring only a small number of processes to produce, and is provided with a gate insulating film having a memory function. The semiconductor storage unit has a semiconductor layer, two diffusion layer regions forming a source region and a drain region, which are formed on the semiconductor layer, a channel region fixed between the two diffusion layer regions, a gate insulating film that is formed on the channel region, and made of a silicon oxide film containing carbon atoms of 0.1 to 5.0 atomic percent, and a gate electrode formed on the gate insulating film.

摘要翻译： 提供具有仅需要少量工艺制造的简单结构的半导体存储单元，并且设置有具有记忆功能的栅极绝缘膜。 半导体存储单元具有半导体层，形成在半导体层上的源极区和漏极区的两个扩散层区域，固定在两个扩散层区域之间的沟道区域，形成在栅极绝缘膜上的栅极绝缘膜 沟道区域，由碳原子数为0.1〜5.0原子％的氧化硅膜构成，栅极形成在栅极绝缘膜上。