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1.发明授权Semiconductor storage device, manufacturing method therefor and portable electronic equipment 有权半导体存储装置及其制造方法及便携式电子设备公开(公告)号：US07315060B2
公开(公告)日：2008-01-01
申请号：US11142770
申请日：2005-06-02
IPC分类号： H01L29/792
CPC分类号： H01L29/6684 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.
摘要翻译： 半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的单个栅电极。 形成在栅电极两侧的第一和第二记忆功能体。 在栅极侧的基板的表面形成P型沟道区。 在沟道区域的两侧形成N型第一和第二扩散区域。 沟道区域由位于第一和第二存储器功能体下面的偏移区域和位于栅电极下方的栅极电极构成。 赋予偏移区域的P型导电性的掺杂剂的浓度有效地低于向区域下方的栅电极施加P型导电性的掺杂剂的浓度。 这使得可以提供容易缩小的半导体存储装置。
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公开(公告)号：US06562699B1
公开(公告)日：2003-05-13
申请号：US09202714
申请日：1998-12-21
申请人： Kotaro Kataoka , Hiroshi Iwata , Masayuki Nakano
发明人： Kotaro Kataoka , Hiroshi Iwata , Masayuki Nakano
IPC分类号： H01L21322
CPC分类号： H01L21/02043 , H01L21/28052 , H01L21/28512 , H01L21/28518 , H01L21/76897 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.
摘要翻译： 通过除去存在于硅层表面和其表面上的卤素原子，使得卤素原子的浓度变为100ppm或更低，并且在所得硅层上形成电极，可以制备具有低电阻的电极， 并且还可以生产高可靠性的半导体器件。
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公开(公告)号：US07135386B2
公开(公告)日：2006-11-14
申请号：US10394024
申请日：2003-03-24
申请人： Kotaro Kataoka , Hiroshi Iwata , Masayuki Nakano
发明人： Kotaro Kataoka , Hiroshi Iwata , Masayuki Nakano
IPC分类号： H01L21/322
CPC分类号： H01L21/02043 , H01L21/28052 , H01L21/28512 , H01L21/28518 , H01L21/76897 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.
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4.发明申请Semiconductor storage device, manufacturing method therefor and portable electronic equipment 有权半导体存储装置及其制造方法及便携式电子设备公开(公告)号：US20050280065A1
公开(公告)日：2005-12-22
申请号：US11142770
申请日：2005-06-02
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/792
CPC分类号： H01L29/6684 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.
摘要翻译： 半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的单个栅电极。 形成在栅电极两侧的第一和第二记忆功能体。 在栅极侧的基板的表面形成P型沟道区。 在沟道区域的两侧形成N型第一和第二扩散区域。 沟道区域由位于第一和第二存储器功能体之下的偏移区域和位于栅电极下方的栅极电极构成。 赋予偏移区域的P型导电性的掺杂剂的浓度有效地低于向区域下方的栅电极施加P型导电性的掺杂剂的浓度。 这使得可以提供容易缩小的半导体存储装置。
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公开(公告)号：US06291861B1
公开(公告)日：2001-09-18
申请号：US09345414
申请日：1999-06-30
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/2257 , H01L27/088 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4941 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/78654
摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
摘要翻译： 具有器件分离区域和有源区域的半导体器件包括栅极氧化膜，源极/漏极区域和电耦合到源极/漏极区域的电极。 有源区在第一面处与栅极氧化膜接触，源/漏区的一部分位于第一面的上方。 电极在第二面处与源极/漏极区域接触，第二面部相对于第一面构成一个角度。
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公开(公告)号：US5960319A
公开(公告)日：1999-09-28
申请号：US699410
申请日：1996-08-19
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26526 , H01L21/28052 , H01L21/28518 , H01L21/823807 , H01L29/665 , Y10S257/90
摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
摘要翻译： 公开了一种半导体器件及其制造方法。 在硅半导体衬底上形成氮化硅膜。 然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。 硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。 制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。
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7.发明申请Semiconductor device having junction depths for reducing short channel effect 审中-公开具有用于降低短沟道效应的结深度的半导体器件公开(公告)号：US20050045962A1
公开(公告)日：2005-03-03
申请号：US10421713
申请日：2003-04-24
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/26506 , H01L21/2652 , H01L21/26526 , H01L21/2658 , H01L21/28052 , H01L21/28518 , H01L21/823807 , H01L29/665 , H01L29/6659
摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
摘要翻译： 公开了一种半导体器件及其制造方法。 在硅半导体衬底上形成氮化硅膜。 然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。 硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。 制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。
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公开(公告)号：US06682966B2
公开(公告)日：2004-01-27
申请号：US10171540
申请日：2002-06-17
IPC分类号： A01L2100
CPC分类号： H01L29/783 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.
摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。
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9.发明授权公开(公告)号：US06677212B1
公开(公告)日：2004-01-13
申请号：US10070478
申请日：2002-05-02
IPC分类号： H01L27108
CPC分类号： H01L29/66598 , H01L21/26586 , H01L21/28525 , H01L29/1083 , H01L29/41766 , H01L29/41775 , H01L29/41783 , H01L29/6659
摘要： A gate oxide film (23), a gate electrode (24) and a gate cap insulating film (25) are stacked on an active region of a p-type semiconductor substrate (21), and an insulating side wall (29) is formed, followed by BF2 ion implantation. Thus, a surface of the p-type semiconductor substrate becomes amorphous so that single-crystal silicon is prevented from epitaxially growing in the next process of depositing polysilicon (33). Halo regions (32) are formed using the BF2 ions having the opposite conductivity to a source/drain to reduce the short-channel effect. The substrate is then passed through a nitrogen purge chamber having a dew point kept at −100° C. to remove water molecules completely, and polysilicon (33) is deposited. Because native oxide is prevented from growing at an interface between the active region and the polysilicon, source/drain regions (34) formed later by implantation and diffusion of n-type impurity ions achieve a uniform junction depth.
摘要翻译： 在p型半导体基板（21）的有源区上层叠有栅极氧化膜（23），栅极电极（24）和栅极绝缘膜（25），形成绝缘侧壁（29） ，然后进行BF2离子注入。 因此，p型半导体衬底的表面变为非晶态，从而在下一个沉积多晶硅的工艺中防止单晶硅外延生长（33）。 使用与源极/漏极具有相反导电性的BF 2离子形成光晕区域（32），以减少短沟道效应。 然后将基底通过具有保持在-100℃的露点的氮气净化室，以完全去除水分子，并沉积多晶硅（33）。 因为防止在有源区和多晶硅之间的界面处生长了自然氧化物，所以随后通过n型杂质离子的注入和扩散而形成的源/漏区（34）达到均匀的结深度。
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10.发明授权公开(公告)号：US06297114B1
公开(公告)日：2001-10-02
申请号：US09205754
申请日：1998-12-04
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/0332 , H01L21/26586 , H01L21/28017 , H01L21/823807 , H01L27/0928 , H01L29/1083 , H01L29/665 , H01L29/7833
摘要： A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity diffusion region. The above semiconductor device is able to suppress the short-channel effects, and reduce the source-drain parasitic resistance and the source-drain junction leakage current while maintaining a small source-drain capacity.
摘要翻译： 一种通过栅极氧化膜在Si衬底上具有栅电极的半导体器件; 具有与阱相反的导电类型的第一杂质扩散区，其将通过栅电极侧壁电介质膜在栅电极的两个相对侧中形成源区和漏区的一部分; 第二杂质扩散区，与栅电极侧壁电介质膜下方的第一杂质扩散区具有相同的导电类型，与栅电极正下方的沟道区相比，比第一杂质扩散区浅; 所述栅极电极上的钛硅化物膜和所述栅电极侧壁电介质膜的两个相对侧中的所述第一杂质扩散区域的所述Si衬底的表面; 和形成在第一杂质扩散区中的第三杂质扩散区，其具有比第一杂质扩散区高的浓度和与第一和第二杂质扩散区相同的导电类型。 上述半导体器件能够抑制短沟道效应，并且在保持较小的源极 - 漏极容量的同时降低源极 - 漏极寄生电阻和源极 - 漏极结漏电流。
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