公开(公告)号：US06004831A

公开(公告)日：1999-12-21

申请号：US862697

申请日：1997-05-23

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/13 ,  H01L21/00 ,  H01L27/12

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电布线的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US5563440A

公开(公告)日：1996-10-08

申请号：US293427

申请日：1994-08-22

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L23/02 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/0922 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78621

摘要： A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

摘要翻译： 不会堵塞的多层半导体集成电路。 电路包括半导体衬底，形成在衬底上的第一MOS晶体管，沉积在第一晶体管上的层间绝缘体和形成在层间绝缘体上的第二MOS晶体管。 两个晶体管具有不同的导电类型。 第二晶体管的栅电极主要由金属或金属硅化物构成，例如， 铝。 栅电极的上表面和侧表面涂覆有包含金属或金属硅化物的氧化物的材料。

公开(公告)号：US5495121A

公开(公告)日：1996-02-27

申请号：US953943

申请日：1992-09-30

申请人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L27/02

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L29/4908 ,  H01L29/78666 ,  H01L29/78675 ,  G02F1/13454 ,  G02F2001/136245

摘要： A semiconductor device or a semiconductor integrated circuit includes a field effect transistor having a source region, a drain region and a channel regions formed within a semiconductor substrate. A lower wiring is formed on the semiconductor substrate to form a gate electrode and its extension and oxidized to form an oxide film covering the lower wiring. An upper wiring is formed over the lower wiring on the semiconductor substrate to make contact with the drain or source region. The lower wiring is electrically insulated from the upper wiring by the oxide film.

摘要翻译： 半导体器件或半导体集成电路包括具有源极区，漏极区和形成在半导体衬底内的沟道区的场效应晶体管。 在半导体基板上形成下布线以形成栅电极，并且其延伸部被氧化以形成覆盖下布线的氧化膜。 在半导体衬底上的下布线之上形成上布线以与漏区或源区接触。 下布线通过氧化膜与上布线电绝缘。

公开(公告)号：US06979840B1

公开(公告)日：2005-12-27

申请号：US08223823

申请日：1994-04-06

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/13 ,  H01L29/04

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电互连的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US5716871A

公开(公告)日：1998-02-10

申请号：US117709

申请日：1993-09-08

申请人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L29/4908 ,  H01L29/78666 ,  H01L29/78675 ,  G02F1/13454 ,  G02F2001/136245

摘要： A semiconductor device or a semiconductor integrated circuit includes a field effect transistor having a source region, a drain region and a channel regions formed within a semiconductor substrate. A lower wiring is formed on the semiconductor substrate to form a gate electrode and its extension and oxidized to form an oxide film covering the lower wiring. An upper wiring is formed over the lower wiring on the semiconductor substrate to make contact with the drain or source region. The lower wiring is electrically insulated from the upper wiring by the oxide film.

摘要翻译： 半导体器件或半导体集成电路包括具有源极区，漏极区和形成在半导体衬底内的沟道区的场效应晶体管。 在半导体基板上形成下布线以形成栅电极，并且其延伸部被氧化以形成覆盖下布线的氧化膜。 在半导体衬底上的下布线之上形成上布线以与漏区或源区接触。 下布线通过氧化膜与上布线电绝缘。

公开(公告)号：US5972742A

公开(公告)日：1999-10-26

申请号：US885872

申请日：1997-06-30

申请人： Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Itaru Koyama ,  Shunpei Yamazaki

发明人： Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Itaru Koyama ,  Shunpei Yamazaki

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L21/823475 ,  H01L21/28079 ,  H01L21/84 ,  Y10S438/911

摘要： An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

摘要翻译： 描述了形成绝缘栅场效应晶体管的改进方法。 根据该方法，栅电极由诸如铝的金属以及电连接栅电极的布线形成。 通过将栅电极作为阳极浸渍在电解质中以形成覆盖它们的金属的氧化物来阳极氧化。 由于在阳极氧化之前用合适的有机膜覆盖连接布线，所以不会在其上形成氧化铝，从而通过通常的蚀刻容易地去除连接布线。

公开(公告)号：US5677559A

公开(公告)日：1997-10-14

申请号：US460426

申请日：1995-07-19

申请人： Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Itaru Koyama ,  Shunpei Yamazaki

发明人： Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Itaru Koyama ,  Shunpei Yamazaki

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/823475 ,  H01L21/28079 ,  H01L21/84 ,  Y10S438/911

摘要： An improved method of forming insulated gate field effect transistors is described. In accordance with the method, gate electrodes are formed from metal such as aluminum together with wirings electrically connecting the gate electrodes. The gate electrodes are anodic oxidized by dipping them as an anode in an electrolyte to form an oxide of the metal covering them. Since the connecting wirings are covered with a suitable organic film before the anodizing, no aluminum oxide is formed thereon so that it is easy to remove the connecting wiring by usual etching.

摘要翻译： 描述了形成绝缘栅场效应晶体管的改进方法。 根据该方法，栅电极由诸如铝的金属以及电连接栅电极的布线形成。 通过将栅电极作为阳极浸渍在电解质中以形成覆盖它们的金属的氧化物来阳极氧化。 由于在阳极氧化之前用合适的有机膜覆盖连接布线，所以不会在其上形成氧化铝，从而通过通常的蚀刻容易地去除连接布线。

公开(公告)号：US07642584B2

公开(公告)日：2010-01-05

申请号：US11206293

申请日：2005-08-18

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电互连的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US20060060852A1

公开(公告)日：2006-03-23

申请号：US11206293

申请日：2005-08-18

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电互连的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US5604137A

公开(公告)日：1997-02-18

申请号：US460632

申请日：1995-06-02

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/84 ,  H01L27/0922 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78621

摘要： A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

摘要翻译： 不会堵塞的多层半导体集成电路。 电路包括半导体衬底，形成在衬底上的第一MOS晶体管，沉积在第一晶体管上的层间绝缘体和形成在层间绝缘体上的第二MOS晶体管。 两个晶体管具有不同的导电类型。 第二晶体管的栅电极主要由金属或金属硅化物构成，例如， 铝。 栅电极的上表面和侧表面涂覆有包含金属或金属硅化物的氧化物的材料。