公开(公告)号：US06979840B1

公开(公告)日：2005-12-27

申请号：US08223823

申请日：1994-04-06

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/13 ,  H01L29/04

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电互连的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US6013928A

公开(公告)日：2000-01-11

申请号：US479393

申请日：1995-06-07

申请人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

发明人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

IPC分类号： G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H04N3/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L29/04

CPC分类号： H04N3/127 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  G02F1/1368 ,  G02F2001/136245 ,  G09G2300/0823

摘要： An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

摘要翻译： 一种适用于有源矩阵液晶显示器的绝缘栅场效应晶体管。 沟道长度或源极区域和漏极区域之间的距离大于沿着沟道的纵向方向取得的栅电极的长度。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场被施加到来自栅电极的这些偏移区域。

公开(公告)号：US5716871A

公开(公告)日：1998-02-10

申请号：US117709

申请日：1993-09-08

申请人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L29/4908 ,  H01L29/78666 ,  H01L29/78675 ,  G02F1/13454 ,  G02F2001/136245

摘要： A semiconductor device or a semiconductor integrated circuit includes a field effect transistor having a source region, a drain region and a channel regions formed within a semiconductor substrate. A lower wiring is formed on the semiconductor substrate to form a gate electrode and its extension and oxidized to form an oxide film covering the lower wiring. An upper wiring is formed over the lower wiring on the semiconductor substrate to make contact with the drain or source region. The lower wiring is electrically insulated from the upper wiring by the oxide film.

摘要翻译： 半导体器件或半导体集成电路包括具有源极区，漏极区和形成在半导体衬底内的沟道区的场效应晶体管。 在半导体基板上形成下布线以形成栅电极，并且其延伸部被氧化以形成覆盖下布线的氧化膜。 在半导体衬底上的下布线之上形成上布线以与漏区或源区接触。 下布线通过氧化膜与上布线电绝缘。

公开(公告)号：US06977392B2

公开(公告)日：2005-12-20

申请号：US10390014

申请日：2003-03-18

申请人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

发明人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

IPC分类号： G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H04N3/12 ,  H01L31/0392

CPC分类号： H01L27/1222 ,  G02F1/1368 ,  G02F2001/136245 ,  G09G2300/0823 ,  H01L27/1214 ,  H01L27/1248 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  H04N3/127

摘要： An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

摘要翻译： 一种适用于有源矩阵液晶显示器的绝缘栅场效应晶体管。 沟道长度或源极区域和漏极区域之间的距离大于沿着沟道的纵向方向取得的栅电极的长度。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场被施加到来自栅电极的这些偏移区域。

公开(公告)号：US06004831A

公开(公告)日：1999-12-21

申请号：US862697

申请日：1997-05-23

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/13 ,  H01L21/00 ,  H01L27/12

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电布线的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US5563440A

公开(公告)日：1996-10-08

申请号：US293427

申请日：1994-08-22

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L23/02 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/0922 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/78621

摘要： A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

摘要翻译： 不会堵塞的多层半导体集成电路。 电路包括半导体衬底，形成在衬底上的第一MOS晶体管，沉积在第一晶体管上的层间绝缘体和形成在层间绝缘体上的第二MOS晶体管。 两个晶体管具有不同的导电类型。 第二晶体管的栅电极主要由金属或金属硅化物构成，例如， 铝。 栅电极的上表面和侧表面涂覆有包含金属或金属硅化物的氧化物的材料。

公开(公告)号：US5495121A

公开(公告)日：1996-02-27

申请号：US953943

申请日：1992-09-30

申请人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Akira Mase ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L27/02

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L29/4908 ,  H01L29/78666 ,  H01L29/78675 ,  G02F1/13454 ,  G02F2001/136245

摘要： A semiconductor device or a semiconductor integrated circuit includes a field effect transistor having a source region, a drain region and a channel regions formed within a semiconductor substrate. A lower wiring is formed on the semiconductor substrate to form a gate electrode and its extension and oxidized to form an oxide film covering the lower wiring. An upper wiring is formed over the lower wiring on the semiconductor substrate to make contact with the drain or source region. The lower wiring is electrically insulated from the upper wiring by the oxide film.

摘要翻译： 半导体器件或半导体集成电路包括具有源极区，漏极区和形成在半导体衬底内的沟道区的场效应晶体管。 在半导体基板上形成下布线以形成栅电极，并且其延伸部被氧化以形成覆盖下布线的氧化膜。 在半导体衬底上的下布线之上形成上布线以与漏区或源区接触。 下布线通过氧化膜与上布线电绝缘。

公开(公告)号：US5485019A

公开(公告)日：1996-01-16

申请号：US014455

申请日：1993-02-03

申请人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

IPC分类号： G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L33/00 ,  H01L29/78

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/78618 ,  G02F2001/136245 ,  G09G2300/0823 ,  Y10S148/161 ,  Y10S148/163

摘要： A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide. In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

摘要翻译： 形成在基板上的布线被氧化，并且氧化物用作用于形成晶体管的源极和漏极杂质区域或用作彼此绝缘布线的材料的掩模，或者用作电容器的电介质。 氧化物的厚度根据氧化物的目的而确定。 在适于用于有源矩阵液晶显示器的晶体管中，沟道长度或源极区域和漏极区域之间的距离大于沿着栅极电极的纵向取向的栅电极的长度 渠道。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场被施加到来自栅电极的这些偏移区域。

公开(公告)号：US07642584B2

公开(公告)日：2010-01-05

申请号：US11206293

申请日：2005-08-18

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电互连的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US06777711B2

公开(公告)日：2004-08-17

申请号：US10390014

申请日：2003-03-18

申请人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

发明人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

IPC分类号： H01L310392

摘要： An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.