公开(公告)号：US12169448B2

公开(公告)日：2024-12-17

申请号：US17551654

申请日：2021-12-15

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Bernd Meyer

IPC: G06F11/36 ,  G06F9/445

Abstract: A device for processing bit strings of a program flow including a data memory and an interface that is designed to output a second bit string, and a bit string manipulator that is designed to analyze the first bit string at a predetermined bit string section for information that indicates a target state of the program flow, and to manipulate the first bit string in the bit string section to obtain the second bit string.

公开(公告)号：US20220188216A1

公开(公告)日：2022-06-16

申请号：US17551654

申请日：2021-12-15

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Bernd Meyer

IPC: G06F11/36 ,  G06F9/445

Abstract: A device for processing bit strings of a program flow including a data memory and an interface that is designed to output a second bit string, and a bit string manipulator that is designed to analyze the first bit string at a predetermined bit string section for information that indicates a target state of the program flow, and to manipulate the first bit string in the bit string section to obtain the second bit string.

公开(公告)号：US10678709B2

公开(公告)日：2020-06-09

申请号：US16253831

申请日：2019-01-22

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel

IPC: G06F12/14 ,  G06F12/10

Abstract: An apparatus for encrypting an input memory address to obtain an encrypted memory address comprises an input interface for receiving the input memory address being an address of a memory. Moreover, the apparatus comprises an encryption module for encrypting the input memory address depending on a cryptographic key to obtain the encrypted memory address. The encryption module is configured to encrypt the input memory address by applying a map mapping the input memory address to the encrypted memory address, wherein the encryption module is configured to apply the map by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective.

公开(公告)号：US10176121B2

公开(公告)日：2019-01-08

申请号：US13942096

申请日：2013-07-15

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel

IPC: G06F12/10 ,  G06F12/14

Abstract: An apparatus for encrypting an input memory address to obtain an encrypted memory address is provided. The apparatus comprises an input interface for receiving the input memory address being an address of a memory. Moreover, the apparatus comprises an encryption module for encrypting the input memory address depending on a cryptographic key to obtain the encrypted memory address. The encryption module is configured to encrypt the input memory address by applying a map mapping the input memory address to the encrypted memory address, wherein the encryption module is configured to apply the map by conducting a multiplication and a modulo operation using the cryptographic key and a divisor of the modulo operation, such that the map is bijective.

公开(公告)号：US20180218177A1

公开(公告)日：2018-08-02

申请号：US15883120

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel

IPC: G06F21/75 ,  H03K19/003 ,  G11C11/412 ,  G11C11/419 ,  H04L9/32 ,  H04L9/08 ,  G06F21/72

CPC classification number: G06F21/75 ,  G06F21/72 ,  G06F21/73 ,  G09C1/00 ,  G11C7/1006 ,  G11C7/24 ,  G11C11/412 ,  G11C11/419 ,  H03K19/00315 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/3278

Abstract: According to one embodiment, a physical uncloneable function circuit for providing a protected output bit is described including at least one physical uncloneable function circuit element configured to output a bit of a physical uncloneable function value, a physical uncloneable function bit output terminal and a coupling circuit connected between the physical uncloneable function circuit element and the physical uncloneable function bit output terminal configured to receive a control signal, supply the bit to the physical uncloneable function bit output terminal for a first state of the control signal and supply the complement of the bit to the physical uncloneable function bit output terminal for a second state of the control signal.

公开(公告)号：US09356604B2

公开(公告)日：2016-05-31

申请号：US13775789

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC: H03K19/20 ,  G11C13/00 ,  H01L27/24

CPC classification number: H03K19/20 ,  G11C13/0004 ,  H01L27/24

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates.

Abstract translation: 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。

公开(公告)号：US20150095660A1

公开(公告)日：2015-04-02

申请号：US14040840

申请日：2013-09-30

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Tomaz Felicijan ,  Stefan Mangard

IPC: G06F21/71 ,  G06F21/72

CPC classification number: G06F21/71 ,  G06F21/445 ,  G06F21/72 ,  G06F2221/2103 ,  G06F2221/2143 ,  H04L9/004

Abstract: A computational system is configured to protect against integrity violation. The computational system includes a processing unit and a critical resource, the critical resource being controllable by the processing unit so as to be locked or unlocked. The critical resource is configured to intermittently transmit a polling value to the processing unit, and the processing unit is configured to apply a transformation onto the polling value so as to obtain a response value and send the response value back to the critical resource. The critical resource is configured to check the response value on correctness so as to obtain a check result, and subject the controllability to a dependency on the check result.

Abstract translation: 计算系统被配置为防止完整性违规。 计算系统包括处理单元和关键资源，关键资源由处理单元控制，以便被锁定或解锁。 关键资源被配置为间歇地向处理单元发送轮询值，并且处理单元被配置为将转换应用于轮询值，以便获得响应值并将响应值发送回关键资源。 配置关键资源以正确性检查响应值，以获得检查结果，并对可检测性进行检查结果的依赖。

公开(公告)号：US20150032992A1

公开(公告)日：2015-01-29

申请号：US14341925

申请日：2014-07-28

Applicant: Infineon Technologies AG

Inventor： Rainer Goettfert ,  Berndt Gammel ,  Gerd Dirscherl

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/3885 ,  G06F21/85

Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

Abstract translation: 提供具有第一处理部件和第二处理部件的处理装置。 第一组件具有第一输出存储器和第二输出存储器以及使用存储要输出的值的第一存储器的控制装置，并且第二存储器存储根据该值的规定函数所基于的值。 每当第二组件读取存储在第一存储器中的值时，控制装置将新的值存储在第一存储器中。 第二组件具有读取存储在第一和第二存储器中的值的读取装置，以及检查从第二存储器读取的值是否根据从第一存储器读取的值的规定函数为基础的处理装置，并且依赖于 在结果上，处理从第一个内存读取的值。

公开(公告)号：US20140169557A1

公开(公告)日：2014-06-19

申请号：US14074279

申请日：2013-11-07

Applicant: Infineon Technologies AG

Inventor： Berndt Gammel ,  Wieland Fischer ,  Stefan Mangard

IPC: H04L9/08 ,  H04L9/06

CPC classification number: H04L9/0869 ,  H04L9/0637 ,  H04L9/0668 ,  H04L9/0866 ,  H04L9/3242

Abstract: A key-generating apparatus is provided for generating a session key which is known to a first communication apparatus and a second communication apparatus, for the first communication apparatus, from secret information which may be determined by the first and second communication apparatuses. The key-generating apparatus includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information, and a second module operable to use the session key for communication with the second communication apparatus.

Abstract translation: 提供了一种密钥生成装置，用于从可由第一和第二通信装置确定的秘密信息生成第一通信装置和第二通信装置已知的会话密钥。 密钥生成装置包括：第一模块，其可操作以使用随机数的至少一部分和所述秘密信息的一部分的级联来计算会话密钥;以及第二模块，其可操作以使用所述会话密钥与所述第二模块进行通信 通信设备。

公开(公告)号：US20130246881A1

公开(公告)日：2013-09-19

申请号：US13803324

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Rainer Goettfert ,  Gerd Dirscherl ,  Berndt Gammel ,  Thomas Kuenemund

IPC: H03M13/00

CPC classification number: H03M13/00 ,  H03M13/03 ,  H03M13/3707 ,  H04L1/0045 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/34

Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.

Abstract translation: 提供了用于重建用于电子设备的物理上不可克隆功能（PUF）A的方法。 该方法包括产生潜在错误的PUF At，并通过存储的校正矢量Deltat-1对潜在错误的PUF At进行初步校正，以获得预先校正的PUF Bt。 通过纠错算法从预先校正的PUF Bt重建PUF A。 还提供了相应的装置。