公开(公告)号：US10692888B2

公开(公告)日：2020-06-23

申请号：US15946666

申请日：2018-04-05

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US10559688B2

公开(公告)日：2020-02-11

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Joodong Park ,  Chia-Hong Jan ,  Hsu-Yu Chang

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

公开(公告)号：US10431661B2

公开(公告)日：2019-10-01

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US10263112B2

公开(公告)日：2019-04-16

申请号：US15353631

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Curtis Tsai ,  Jeng-Ya D. Yeh ,  Joodong Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

公开(公告)号：US10096599B2

公开(公告)日：2018-10-09

申请号：US14977367

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Curtis Tsai ,  Chia-Hong Jan ,  Jeng-Ya David Yeh ,  Joodong Park ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US09881927B2

公开(公告)日：2018-01-30

申请号：US14780222

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Walid M. Hafez ,  Joodong Park

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/112 ,  H01L29/66 ,  H01L23/525 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/11206 ,  H01L21/823431 ,  H01L23/5256 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.

公开(公告)号：US09786783B2

公开(公告)日：2017-10-10

申请号：US13995717

申请日：2013-03-29

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments.