Patent search ap:("INTEL CORPORATION") AND inv:"Justin E. Gottschlich" Page 4

31.

发明授权
Coordination and increased utilization of graphics processors during inference 有权

公开(公告)号：US10304154B2

公开(公告)日：2019-05-28

申请号：US15495054

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu , Altug Koker , John C. Weast , Mike B. Macpherson , Linda L. Hurd , Sara S. Baghsorkhi , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Liwei Ma , Elmoustapha Ould-Ahmed-Vall , Kamal Sinha , Joydeep Ray , Balaji Vembu , Sanjeev Jahagirdar , Vasanth Ranganathan , Dukhwan Kim

IPC: G06T1/20 , G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

32.

发明授权
Extend GPU/CPU coherency to multi-GPU cores 有权

公开(公告)号：US10261903B2

公开(公告)日：2019-04-16

申请号：US15489149

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel , Prasoonkumar Surti , John C. Weast , Sara S. Baghsorkhi , Justin E. Gottschlich , Abhishek R. Appu , Nicolas C. Galoppo Von Borries , Joydeep Ray , Narayan Srinivasa , Feng Chen , Ben J. Ashbaugh , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Eriko Nurvitadhi , Balaji Vembu , Altug Koker

IPC: G06F12/0837 , G06N3/08 , G06N20/00 , G06T1/20

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

33.

发明申请
METHODS AND APPARATUS TO GENERATE ANOMALY DETECTION DATASETS 审中-公开

公开(公告)号：US20180330253A1

公开(公告)日：2018-11-15

申请号：US15591886

申请日：2017-05-10

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich , Naila Farooqui

IPC: G06N5/04 , G06N99/00

CPC classification number: G06N5/047 , G06N99/005

Abstract: Example methods and apparatus to generate anomaly detection datasets are disclosed. An example method to generate an anomaly detection dataset for training a machine learning model to detect real world anomalies includes receiving a user definition of an anomaly generator function, executing, with a processor, the anomaly generator function to generate user-defined anomaly data, and combining the user-defined anomaly data with nominal data to generate the anomaly detection dataset.

34.

发明申请
COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE 审中-公开

公开(公告)号：US20180308202A1

公开(公告)日：2018-10-25

申请号：US15495054

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu , Altug Koker , John C. Weast , Mike B. Macpherson , Linda L. Hurd , Sara S. Baghsorkhi , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Liwei Ma , Elmoustapha Ould-Ahmed-Vall , Kamal Sinha , Joydeep Ray , Balaji Vembu , Sanjeev Jahagirdar , Vasanth Ranganathan , DUKHWAN Kim

IPC: G06T1/20 , G06N3/08

CPC classification number: G06T1/20 , G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

35.

发明申请
DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS 审中-公开

公开(公告)号：US20180307984A1

公开(公告)日：2018-10-25

申请号：US15494971

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Altug Koker , Abhishek R. Appu , Kamal Sinha , Joydeep Ray , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Anbang Yao , Kevin Nealis , Xiaoming Chen , John C. Weast , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Farshad Akhbari , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy , Vasanth Ranganathan , Sanjeev Jahagirdar

IPC: G06N3/08 , G06N99/00

CPC classification number: G06N3/08 , G06F9/28 , G06F9/505 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N99/005

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

36.

发明授权
Technologies for root cause identification of use-after-free memory corruption bugs 有权

公开(公告)号：US09864649B2

公开(公告)日：2018-01-09

申请号：US14670863

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira

IPC: G06F11/00 , G06F11/07

CPC classification number: G06F11/079 , G06F11/073

Abstract: Technologies for identification of a potential root cause of a use-after-free memory corruption bug of a program include a computing device to replay execution of the execution of the program based on an execution log of the program. The execution log comprises an ordered set of executed instructions of the program that resulted in the use-after-free memory corruption bug. The computing device compares a use-after-free memory address access of the program to a memory address associated with an occurrence of the use-after-free memory corruption bug in response to detecting the use-after-free memory address access and records the use-after-free memory address access of the program as a candidate for a root cause of the use-after-free memory corruption bug to a candidate list in response to detecting a match between the use-after-free memory address access of the program and the memory address associated with the occurrence of the use-after-free memory corruption bug.

37.

发明授权
Replay execution of instructions in thread chunks in the chunk order recorded during previous execution 有权
Title translation: 在先前执行过程中记录的块顺序中重新执行线程块中的指令

公开(公告)号：US09317297B2

公开(公告)日：2016-04-19

申请号：US13629131

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich , Klaus Danne , Cristiano L. Pereira , Gilles A. Pokam , Rolf Kassa , Shiliang Hu , Tim Kranich

IPC: G06F9/44 , G06F9/38 , G06F9/455 , G06F11/30 , G06F11/36 , G06F11/34 , G06F9/52

CPC classification number: G06F9/3005 , G06F9/30072 , G06F9/3802 , G06F9/3851 , G06F9/44 , G06F9/455 , G06F9/52 , G06F11/30 , G06F11/3414 , G06F11/3476 , G06F11/36 , G06F11/3664 , G06F11/3688 , G06F2201/815 , G06F2201/825 , G06F2201/865

Abstract: Embodiments may provide a method for performing a replay of a previous execution of a program. The method includes generating an order of recorded chunks of instructions across a plurality of recorded threads based, at least in part, on log files generated from the previous execution of the program. The method includes initiating execution of the program, the executing program having a plurality of threads, each thread having a number of chunks of instructions. The method includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk before the instruction is executed. The method includes determining, by a replay module executing on the processor, that the chunk is an active chunk if the chunk is currently in line for execution according to the order of recorded chunks, and responsive to a determination that the chunk is the active chunk, executing the instruction.

Abstract translation: 实施例可以提供用于执行程序的先前执行的重放的方法。该方法包括至少部分地基于从先前执行的程序生成的日志文件来生成跨多个记录的线程的所记录的指令块的顺序。该方法包括启动程序的执行，执行程序具有多个线程，每个线程具有多个指令块。该方法包括在执行指令之前由在处理器上执行的虚拟机单元截取块的指令。该方法包括通过在处理器上执行的重放模块来确定，如果该组块当前正在与行记录在一起以便执行，则根据所记录的块的顺序来确定该块是活动块，并且响应于该块是活动块的确定执行指令。

38.

发明申请
PROGRAMMABLE COARSE GRAINED AND SPARSE MATRIX COMPUTE HARDWARE WITH ADVANCED SCHEDULING 有权

公开(公告)号：US20250061534A1

公开(公告)日：2025-02-20

申请号：US18819073

申请日：2024-08-29

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Nadathur Rajagopalan Satish , Jeremy Bottleson , Farshad Akhbari , Altug Koker , Narayan Srinivasa , Dukhwan Kim , Sara S. Baghsorkhi , Justin E. Gottschlich , Feng Chen , Elmoustapha Ould-Ahmed-Vall , Kevin Nealis , Xiaoming Chen , Anbang Yao

IPC: G06T1/20 , G06F9/30 , G06F9/38 , G06N3/04 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/08 , G06N3/084

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.