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公开(公告)号：US09632784B2
公开(公告)日：2017-04-25
申请号：US14562637
申请日：2014-12-05
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
IPC: G06F9/30 , G06F9/38 , G06F7/06 , G06F12/0875 , G06F9/34
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A processor includes a decoder logic to decode a compare instruction, and an execution unit to execute the compare instruction. The compare instruction is to cause the processor to determine whether each 32-bit floating point data element of first and second SIMD floating point operands is valid, compare only valid 32-bit floating point data elements of the first 64-bit SIMD floating point operand with only valid 32-bit floating point data elements of the second 64-bit SIMD floating point operand in the same data element position, and store indicators of whether the compared valid 32-bit floating point data elements of the first and second 64-bit SIMD floating point operands are equal.
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公开(公告)号：US09495160B2
公开(公告)日：2016-11-15
申请号：US14562618
申请日：2014-12-05
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and program means for performing a string comparison operation. An apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
Abstract translation: 用于执行字符串比较操作的方法，装置和程序装置。 一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源分别存储对应于第一和第二文本串的第一和第二操作数的每个数据元素之间的比较结果。
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公开(公告)号：US09448802B2
公开(公告)日：2016-09-20
申请号：US13843576
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and machine-readable medium for performing a string comparison operation. An apparatus includes execution resources to execute a first instruction. In response to the first instruction, the execution resources store a result of a comparison between each data element of a first and second operands corresponding to a first and second text strings, respectively.
Abstract translation: 用于执行字符串比较操作的方法，装置和机器可读介质。 一种装置包括执行第一指令的执行资源。 响应于第一指令，执行资源分别存储对应于第一和第二文本串的第一和第二操作数的每个数据元素之间的比较结果。
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公开(公告)号：US20160248580A1
公开(公告)日：2016-08-25
申请号：US14984616
申请日：2015-12-30
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20160119126A1
公开(公告)日：2016-04-28
申请号：US14984637
申请日：2015-12-30
Applicant: Intel Corporation
Inventor： Gueron Shay , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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Patent Agency Ranking
公开(公告)号：US20160119125A1
公开(公告)日：2016-04-28
申请号：US14984629
申请日：2015-12-30
Applicant: Intel Corporation
Inventor： Gueron Shay , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150169473A1
公开(公告)日：2015-06-18
申请号：US14572545
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150106592A1
公开(公告)日：2015-04-16
申请号：US14576124
申请日：2014-12-18
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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公开(公告)号：US20150106591A1
公开(公告)日：2015-04-16
申请号：US14576101
申请日：2014-12-18
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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公开(公告)号：US20150104009A1
公开(公告)日：2015-04-16
申请号：US14572593
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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