公开(公告)号：US20130217202A1

公开(公告)日：2013-08-22

申请号：US13830282

申请日：2013-03-14

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130161789A1

公开(公告)日：2013-06-27

申请号：US13738914

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Karthik Ramani ,  Sandra Malhotra ,  Hiroyuki Ode

IPC: H01L29/92

CPC classification number: H01L28/40 ,  H01L28/60 ,  H01L28/65 ,  H01L29/92

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.

Abstract translation: 公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。 第一电极由导电二元金属形成。 在第一电极上形成电介质层。 对电介质层进行几毫秒的退火工艺，以使介电材料结晶并降低氧空位的浓度。

公开(公告)号：US20130154057A1

公开(公告)日：2013-06-20

申请号：US13738794

申请日：2013-01-10

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

Abstract translation: 公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。 第一电极由导电二元金属化合物形成，并且导电二元金属化合物在还原气氛中退火以促进所需晶体结构的形成。 二元金属化合物可以是金属氧化物。 在还原气氛中退火金属氧化物（即氧化钼）可导致形成具有金红石相晶体结构的第一电极材料（即MoO 2）。 当使用TiO 2作为电介质层时，这有助于金红石相晶体结构的形成。 TiO 2的金红石相具有比其他可能的TiO 2晶体结构更高的k值，从而改善了DRAM电容器的性能。

公开(公告)号：US20130140675A1

公开(公告)日：2013-06-06

申请号：US13738901

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Sandra Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括：形成第一电极层，在第一电极层上形成催化层，任选地退火催化层，在催化层上形成电介质层， 在电介质层上形成第二电极层，并且可选地对电容器堆叠进行退火。 有利地，电极层是TiN，催化剂层是MoO 2-x，其中x在0和2之间，催化层的物理厚度在约0.5nm和约10nm之间，并且电介质层是ZrO 2。

公开(公告)号：US20130127015A1

公开(公告)日：2013-05-23

申请号：US13738831

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra Malhotra ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 化合物高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

公开(公告)号：US20130056851A1

公开(公告)日：2013-03-07

申请号：US13664922

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01B5/00 ,  H01L29/92

CPC classification number: H01L28/65 ,  H01L28/75

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract translation: 形成用于MIM DRAM电容器的金属氧化物双层第二电极，其中与电介质层（即，底层）接触的电极层具有期望的组成和晶体结构。 如果电介质层是金红石相中的TiO 2，那么结晶MoO2就是一个例子。 双层的另一部分（即顶层）是与底层相同的材料的次氧化物。 顶层用于在随后的PMA或其它DRAM制造步骤期间通过与任何氧物种反应而在它们可以到达双层第二电极的底层之前保护底层免受氧化。

公开(公告)号：US09224878B2

公开(公告)日：2015-12-29

申请号：US13727962

申请日：2012-12-27

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

IPC: H01L21/20 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52 ,  H01L51/00

CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

公开(公告)号：US08975633B2

公开(公告)日：2015-03-10

申请号：US13664922

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/00 ,  H01L29/12 ,  H01L29/786 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L28/75

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract translation: 形成用于MIM DRAM电容器的金属氧化物双层第二电极，其中与电介质层（即，底层）接触的电极层具有期望的组成和晶体结构。 如果电介质层是金红石相中的TiO 2，那么结晶MoO2就是一个例子。 双层的另一部分（即顶层）是与底层相同的材料的次氧化物。 顶层用于在随后的PMA或其它DRAM制造步骤期间通过与任何氧物种反应而在它们可以到达双层第二电极的底层之前保护底层免受氧化。

公开(公告)号：US08836002B2

公开(公告)日：2014-09-16

申请号：US13738794

申请日：2013-01-10

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/94 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

公开(公告)号：US08652927B2

公开(公告)日：2014-02-18

申请号：US13738510

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L21/20

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。