公开(公告)号：US20180348838A1

公开(公告)日：2018-12-06

申请号：US15939101

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Uksong KANG

IPC: G06F1/32 ,  G06F3/06

Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.

公开(公告)号：US20180136866A1

公开(公告)日：2018-05-17

申请号：US15811497

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Dean-Dexter R. EUGENIO ,  Arvind KUMAR ,  John R. GOLES ,  Christopher E. COX

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0635 ,  G06F3/0679 ,  G06F11/22 ,  G06F13/1673 ,  G06F13/1689

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

公开(公告)号：US20180121123A1

公开(公告)日：2018-05-03

申请号：US15721516

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Christopher P. MOZAK ,  Christopher E. COX

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/028

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

公开(公告)号：US20170169881A1

公开(公告)日：2017-06-15

申请号：US15354200

申请日：2016-11-17

Applicant: INTEL CORPORATION

Inventor： Christopher E. COX ,  Kuljit Singh BAINS ,  John B. HALBERT

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.