公开(公告)号：US11023244B2

公开(公告)日：2021-06-01

申请号：US15713974

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Ee Loon Teoh ,  Eng Hun Ooi ,  Roger K. Cheng

IPC: G06F9/38 ,  G06F13/20 ,  G06F13/42 ,  G06F1/32 ,  G06F11/07 ,  G06F13/40 ,  G06F11/30

Abstract: In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.

公开(公告)号：US10942672B2

公开(公告)日：2021-03-09

申请号：US16422827

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Shrinivas Venkatraman ,  Eng Hun Ooi ,  Sahar Khalili ,  Dimpesh Patel ,  Kuan Hua Tan

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42

Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

公开(公告)号：US20190095554A1

公开(公告)日：2019-03-28

申请号：US15718110

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Su Wei Lim ,  Kuan Hua Tan ,  Prashanth Kalluraya

IPC: G06F17/50 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

公开(公告)号：US10127184B2

公开(公告)日：2018-11-13

申请号：US15277893

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Eng Hun Ooi ,  Su Wei Lim

IPC: H03M13/11 ,  G06F13/42 ,  G06F11/10 ,  G06F11/34 ,  G06F11/30

Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

公开(公告)号：US20160034345A1

公开(公告)日：2016-02-04

申请号：US14775848

申请日：2014-02-26

Applicant: Robert J. ROYER, JR. ,  Blaise FANNING ,  Eng Hun OOI ,  INTEL CORPORATION

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控​​制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。

公开(公告)号：US09116694B2

公开(公告)日：2015-08-25

申请号：US13627779

申请日：2012-09-26

Applicant: Intel Corporation

Inventor： Eng Hun Ooi

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/325 ,  G06F1/3268 ,  Y02D10/154 ,  Y02D50/20

Abstract: Embodiments of the invention describe methods, apparatuses and systems for providing an efficient low power exit sequence for peripheral devices. In embodiments of the invention, a signal from a host device is transmitted to a SATA peripheral device for exiting a low-power state. An initialization time for OOB transmission and reception logic of the SATA peripheral device is tracked, and a reference time value based on the tracked initialization time is stored. In subsequent transitions from said low-power state, the reference time value for waking a host physical layer is utilized, thereby improving the efficiency of the management and use of said low power state. In some embodiments, the above described tracked initialization comprises a time from a transmission of an OOB signal (from the host to the peripheral device) to receiving an OOB response at the host device from the SATA peripheral device.

Abstract translation: 本发明的实施例描述了用于为外围设备提供有效的低功率出口序列的方法，装置和系统。 在本发明的实施例中，来自主机设备的信号被传送到SATA外围设备以退出低功率状态。 跟踪SATA外围设备的OOB发送和接收逻辑的初始化时间，并且存储基于追踪的初始化时间的基准时间值。 在从所述低功率状态的后续转换中，利用用于唤醒主机物理层的参考时间值，从而提高所述低功率状态的管理和使用的效率。 在一些实施例中，上述跟踪的初始化包括从OOB信号（从主机到外围设备）的传输到在主机设备处从SATA外围设备接收OOB响应的时间。