公开(公告)号：US20190006508A1

公开(公告)日：2019-01-03

申请号：US15993535

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Daniel B. AUBERTINE ,  Subhash M. JOSHI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/304 ,  H01L27/105 ,  H01L27/088 ,  H01L21/306 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

公开(公告)号：US20160336447A1

公开(公告)日：2016-11-17

申请号：US15220355

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Anand MURTHY ,  Boyan BOYANOV ,  Glenn A. GLASS ,  Thomas HOFFMAN

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/36 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.