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    MULTI-KEY CRYPTOGRAPHIC MEMORY PROTECTION
    31.
    发明申请
    MULTI-KEY CRYPTOGRAPHIC MEMORY PROTECTION 有权

    公开(公告)号：US20210224202A1

    公开(公告)日：2021-07-22

    申请号：US17222722

    申请日：2021-04-05

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Hormuzd M. Khosravi ,  Gideon Gerzon ,  Barry E. Huntley ,  Gilbert Neiger ,  Ido Ouziel ,  Baiju Patel ,  Ravi L. Sahita ,  Amy L. Santoni ,  Ioannis T. Schoinas

    IPC: G06F12/14 ,  H04L29/06 ,  H04L9/06 ,  H04L9/08

    Abstract: In one embodiment, an apparatus comprises a processor to execute instruction(s), wherein the instructions comprise a memory access operation associated with a memory location of a memory. The apparatus further comprises a memory encryption controller to: identify the memory access operation; determine that the memory location is associated with a protected domain, wherein the protected domain is associated with a protected memory region of the memory, and wherein the protected domain is identified from a plurality of protected domains associated with a plurality of protected memory regions of the memory; identify an encryption key associated with the protected domain; perform a cryptography operation on data associated with the memory access operation, wherein the cryptography operation is performed based on the encryption key associated with the protected domain; and return a result of the cryptography operation, wherein the result is to be used for the memory access operation.

    CRYPTOGRAPHIC SYSTEM MEMORY MANAGEMENT
    33.
    发明申请
    CRYPTOGRAPHIC SYSTEM MEMORY MANAGEMENT 审中-公开

    公开(公告)号：US20200177392A1

    公开(公告)日：2020-06-04

    申请号：US16689575

    申请日：2019-11-20

    Applicant: INTEL CORPORATION

    Inventor： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

    IPC: H04L9/32 ,  G06F12/14 ,  G06F21/78 ,  G06F11/10 ,  H04L9/06 ,  H04L9/08 ,  G06F21/79 ,  G06F12/0886 ,  G06F3/06 ,  G11C29/52

    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

    PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE
    35.
    发明申请
    PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中提供多个引脚

    公开(公告)号：US20160357700A1

    公开(公告)日：2016-12-08

    申请号：US14880443

    申请日：2015-10-12

    Applicant: Intel Corporation

    Inventor： Michael T. Klinglesmith ,  Chang Yong Kang ,  Robert DeGruijl ,  Ioannis T. Schoinas ,  Darren Abramson ,  Khee Wooi Lee

    IPC: G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  G06F3/06

    CPC classification number: G06F13/4282 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/068 ,  G06F12/0828 ,  G06F13/1663 ,  G06F2212/621

    Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，系统包括：与第一根空间标识符相关联并包括至少一个第一主处理器和第一代理的第一根空间，所述至少一个第一主处理器和与第一根空间标识符相关联的第一代理 ; 与第二根空间标识符相关联并且包括至少一个第二主处理器和第二代理的第二根空间，所述至少一个第二主处理器和与所述第二根空间标识符相关联的第二代理; 以及共享结构，用于耦合第一根空间和第二根空间，共享结构至少部分地基于事务的根空间字段将事务路由到第一根空间或第二根空间。 描述和要求保护其他实施例。

    SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT
    38.
    发明申请
    SECURE STREAM PROTOCOL FOR SERIAL INTERCONNECT 审中-公开

    公开(公告)号：US20190306134A1

    公开(公告)日：2019-10-03

    申请号：US16445019

    申请日：2019-06-18

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Siddhartha Chhabra ,  David J. Harriman ,  Raghunandan Makaram ,  Ioannis T. Schoinas

    IPC: H04L29/06 ,  G06F21/60 ,  G06F21/64 ,  G06F13/42

    Abstract: Methods, systems, and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed. An apparatus comprises a first device comprising circuitry to, using an end-to-end protocol, secure a transaction in a first secure stream based at least in part on a transaction type of the transaction, where the first secure stream is separate from a second secure stream. The first device is further to send the transaction secured in the first secure stream to a second device over a link established between the first device and the second device, where the transaction is to traverse one or more intermediate devices from the first device to the second device. In more specific embodiments, the first secure stream is based on one of a posted transaction type, a non-posted transaction type, or completion transaction type.

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