公开(公告)号：US20190103872A1

公开(公告)日：2019-04-04

申请号：US16146849

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US20190050604A1

公开(公告)日：2019-02-14

申请号：US16020805

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Andrew Martyn Draper ,  David Goldman

IPC: G06F21/76 ,  G06F21/73 ,  G06F7/58 ,  H03M13/27

Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.

公开(公告)号：US20190042529A1

公开(公告)日：2019-02-07

申请号：US16146886

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F15/76 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.

公开(公告)号：US20240396555A1

公开(公告)日：2024-11-28

申请号：US18797325

申请日：2024-08-07

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/17758 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17796

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US20240205167A1

公开(公告)日：2024-06-20

申请号：US18587744

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H01L23/538 ,  H01L25/065 ,  H04L49/15

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L23/5386 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US20230208783A1

公开(公告)日：2023-06-29

申请号：US18177417

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H01L25/065 ,  H04L49/15

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L2225/06517 ,  H01L23/5386

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US11632112B2

公开(公告)日：2023-04-18

申请号：US15855419

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Sean R. Atsatt ,  Scott J. Weber

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/0175 ,  G06F3/06 ,  G11C11/417 ,  H01L25/18 ,  H01L27/02 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  G11C7/10 ,  H03K19/17796 ,  G11C5/04 ,  G06F30/34

Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

公开(公告)号：US11625245B2

公开(公告)日：2023-04-11

申请号：US16146586

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F9/30 ,  G05B19/05 ,  G06N3/02 ,  G06F15/78 ,  G06F30/34 ,  G06F30/39

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

公开(公告)号：US20220294454A1

公开(公告)日：2022-09-15

申请号：US17710628

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/17758 ,  H03K19/1776 ,  H03K19/17796 ,  H03K19/17772 ,  H03K19/17768

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US20190044515A1

公开(公告)日：2019-02-07

申请号：US15855419

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Sean R. Atsatt ,  Scott J. Weber

IPC: H03K19/0175 ,  G06F3/06 ,  G11C11/417 ,  H01L25/18 ,  H01L27/02 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367

Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.