公开(公告)号：US5301330A

公开(公告)日：1994-04-05

申请号：US596549

申请日：1990-10-12

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F13/368 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F13/368

摘要： Contention handling apparatus which receives access request signals from a number of users and processes these requests to allow controlled access to a shared resource. The contention handling apparatus includes a number of access blocks, with one of the access blocks being associated with each user. A busy line of each of the access blocks is connected to receive a busy signal; the busy signal being an access request signal from a higher priority user, thereby indicating that the shared resource is unavailable. Each access block receiving a busy signal, latches the corresponding access request signal until the busy signal is deasserted. If the busy signal and the access request signal occur at the same time, the corresponding access block generates a wait output signal. The logical sum of the wait output of an access block associated with a next higher priority user and the access request signals of all the higher priority users serves as the busy signal for one of the access blocks.

摘要翻译： 竞争处理装置，其从多个用户接收访问请求信号并处理这些请求以允许对共享资源的受控访问。 争用处理装置包括多个访问块，其中一个访问块与每个用户相关联。 每个接入块的忙线被连接以接收忙信号; 忙信号是来自较高优先权用户的访问请求信号，从而指示共享资源不可用。 每个访问块接收忙信号，锁存相应的访问请求信号，直到忙信号被无效。 如果忙信号和访问请求信号同时发生，则对应的访问块产生等待输出信号。 与下一较高优先级用户相关联的接入块的等待输出和所有较高优先级用户的接入请求信号的逻辑和用作其中一个接入块的忙信号。

公开(公告)号：US4940908A

公开(公告)日：1990-07-10

申请号：US343623

申请日：1989-04-27

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： H03K17/693 ,  H03K19/017 ,  H03K19/0948

CPC分类号： H03K19/01707

摘要： A method and apparatus is disclosed for reducing the propagation delay associated with the critical speed path of a binary logic circuit by using "multiplexing logic". More specifically, the inputs to the logic circuit are defined as either critical or non-critical inputs and the product terms are manipulated so that the non-critical inputs are mutually exclusive. The non-critical inputs are supplied to one or more first logic gate structures wherein the ultimate outputs of the first logic gate structures control multiplexer couplers. The critical speed inputs are supplied to one or more second logic gate structures wherein the ultimate outputs of the second logic gate structures are provided as the input to the multiplexer couplers.

公开(公告)号：US08984254B2

公开(公告)日：2015-03-17

申请号：US13630346

申请日：2012-09-28

申请人： Thang M. Tran ,  Edmund J. Gieske

发明人： Thang M. Tran ,  Edmund J. Gieske

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  Y02D10/13

摘要： A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.

摘要翻译： 一种用于操作处理器的技术包括：通过翻译后备缓冲器中的第一入口号，使用关联的转换后备缓冲器将第一虚拟地址翻译成第一物理地址。 该技术还包括通过翻译后备缓冲器中的第二入口号将翻译后备缓冲器翻译成第二虚拟地址转换为第二物理地址。 该技术还包括响应于第一入口号与第二入口号相同，确定第一和第二虚拟地址指向存储器中相同的物理地址并引用相同的数据。

公开(公告)号：US08966232B2

公开(公告)日：2015-02-24

申请号：US13370420

申请日：2012-02-10

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/1027 ,  G06F2212/1016

摘要： In some embodiments, a data processing system includes a processing unit, a first load/store unit LSU and a second LSU configured to operate independently of the first LSU in single and multi-thread modes. A first store buffer is coupled to the first and second LSUs, and a second store buffer is coupled to the first and second LSUs. The first store buffer is used to execute a first thread in multi-thread mode. The second store buffer is used to execute a second thread in multi-thread mode. The first and second store buffers are used when executing a single thread in single thread mode.

摘要翻译： 在一些实施例中，数据处理系统包括处理单元，第一加载/存储单元LSU和被配置为以单线程和多线程模式独立于第一LSU操作的第二LSU。 第一存储缓冲器耦合到第一和第二LSU，并且第二存储缓冲器耦合到第一和第二LSU。 第一个存储缓冲区用于在多线程模式下执行第一个线程。 第二个存储缓冲区用于在多线程模式下执行第二个线程。 当在单线程模式下执行单个线程时，使用第一个和第二个存储缓冲区。

公开(公告)号：US20130297912A1

公开(公告)日：2013-11-07

申请号：US13462993

申请日：2012-05-03

申请人： Thang M. Tran ,  Sourav Roy

发明人： Thang M. Tran ,  Sourav Roy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3885

摘要： A processor reduces the likelihood of stalls at an instruction pipeline by dynamically extending the size of a full execution queue. To extend the full execution queue, the processor temporarily repurposes another execution queue to store instructions on behalf of the full execution queue. The execution queue to be repurposed can be selected based on a number of factors, including the type of instructions it is generally designated to store, whether it is empty of other instruction types, and the rate of cache hits at the processor. By selecting the repurposed queue based on dynamic factors such as the cache hit rate, the likelihood of stalls at the dispatch stage is reduced for different types of program flows, improving overall efficiency of the processor.

摘要翻译： 处理器通过动态扩展完整执行队列的大小来减少指令流水线停顿的可能性。 为了扩展完整执行队列，处理器暂时重新使用另一个执行队列来代表完整执行队列存储指令。 可以基于许多因素来选择要重新利用的执行队列，包括其通常指定存储的指令的类型，其是否为空其他指令类型，以及处理器处的高速缓存命中率。 通过基于诸如高速缓存命中率的动态因素来选择重新使用的队列，针对不同类型的节目流，调度阶段的停顿的可能性降低，从而提高了处理器的整体效率。

公开(公告)号：US07330936B2

公开(公告)日：2008-02-12

申请号：US11109163

申请日：2005-04-19

申请人： Thang M. Tran ,  Muralidharan S. Chinnakonda ,  Rajinder P. Singh

发明人： Thang M. Tran ,  Muralidharan S. Chinnakonda ,  Rajinder P. Singh

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  G06F2212/1028 ,  Y02D10/13

摘要： A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.

摘要翻译： 一种用于高效内存缓存的系统和方法。 一些说明性实施例可以包括：系统，其包括：耦合到地址总线的散列地址发生器（所述散列地址生成器将存在于所述地址总线上的总线地址转换为当前散列的地址）; 耦合到所述地址总线的高速缓存存储器（所述高速缓冲存储器包括存储在多个标签高速缓存路径中的一个中的标签和存储在多个数据高速缓存路径之一中的数据）; 以及耦合到地址总线的散列存储器（散列存储器包括保存的散列地址，与数据和标签相关联的保存的散列地址）。 当当前散列的地址与保存的散列地址匹配时，小于所有多个标签高速缓存方式被启用。 启用的标签缓存方式包括标签。

公开(公告)号：US6076146A

公开(公告)日：2000-06-13

申请号：US310356

申请日：1999-05-12

申请人： Thang M. Tran ,  Karthikeyan Muthusamy ,  Rammohan Narayan ,  Andrew McBride

发明人： Thang M. Tran ,  Karthikeyan Muthusamy ,  Rammohan Narayan ,  Andrew McBride

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F9/382 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

摘要： An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.

摘要翻译： 提供采用高速缓存保持寄存器的指令高速缓存器。 当从主存储器取出指令字节的高速缓存行时，指令字节从主存储器接收时临时存储到高速缓存保持寄存器中。 指令字节是从主存储器接收到的预解码的。 如果遇到预测的分支指令，则指令高速缓存内的指令获取机制开始从目标指令路径获取指令。 可以在接收到包含预测的分支指令的完整高速缓存行之前启动该获取。 只要从目标指令路径获取的指令继续命中指令高速缓存，可以将这些指令提取并分派到采用指令高速缓存的微处理器中。 由高速缓存保持寄存器接收包含预测的分支指令的指令字节的高速缓存行的剩余部分。 为了减少用于存储高速缓存行指令的指令字节存储器所使用的端口数量，高速缓存保持寄存器保持高速缓存行直到在指令字节存储器中发生空闲周期。 通常用于提取指令的相同端口用于将高速缓存行存储到指令字节存储器中。 在一个实施例中，指令高速缓存将后续的高速缓存行预取到丢失的高速缓存行。 采用第二高速缓存保存寄存器来存储预取的高速缓存行。

公开(公告)号：US6032251A

公开(公告)日：2000-02-29

申请号：US78213

申请日：1998-05-13

申请人： Thang M. Tran ,  David B. Witt

发明人： Thang M. Tran ,  David B. Witt

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A computer system including a microprocessor employing a reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration. Concurrently decoded instructions are stored into a line of storage, and the concurrently decoded instructions are retired as a unit. A last in line (LIL) indication is stored for each instruction in the line. The LIL indication indicates whether or not the instruction is last within the line storing that instruction to update the storage location defined as the destination of that instruction. The LIL indications for a line can be used as write enables for the register file.

摘要翻译： 提供一种包括使用重排序缓冲器的微处理器的计算机系统，其存储对应于每个指令的最后一个缓冲器（LIB）指示。 缓冲器指示中的最后一个指示是否以缓冲器中的指令的程序顺序最后的相应指令是否更新被定义为该指令的目的地的存储位置。 LIB指示包含在依赖关系检查比较中。 如果操作数指定符匹配，并且对应的LIB指示指示对应于目的地操作数的指令最后更新相应的存储位置，则对重定序缓冲器内的给定源操作数和目的地操作数指示依赖关系。 对于给定的源操作数，最多的一个依赖比较可以表示依赖。 根据一个实施例，重排序缓冲器采用线路定向配置。 同时解码的指令被存储到一行存储器中，同时解码的指令作为一个单元退休。 对于行中的每条指令，存储最后一行（LIL）指示。 LIL指示指示在存储该指令的行的最后一条指令是否更新被定义为该指令的目的地的存储位置。 一行的LIL指示可用作寄存器文件的写使能。

公开(公告)号：US6016533A

公开(公告)日：2000-01-18

申请号：US991846

申请日：1997-12-16

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0864 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3842 ,  G06F2212/6082

摘要： A set-associative cache memory configured to use multiple portions of a requested address in parallel to quickly access data from a data array based upon stored way predictions. The cache memory comprises a plurality of memory locations, a plurality of storage locations configured to store way predictions, a decoder, a plurality of pass transistors, and a sense amp unit. A subset of the storage locations are selected according to a first portion of a requested address. The decoder is configured to receive and decode a second portion of the requested address. The decoded portion of the address is used to select a particular subset of the data array based upon the way predictions stored within the selected subset of storage locations. The pass transistors are configured select a second subset of the data array according to a third portion of the requested address. The sense amp unit then reads a cache line from the intersection of the first subset and second subset within the data array.

摘要翻译： 一种组合高速缓存存储器，其被配置为使用所请求地址的多个部分并行地基于存储的方式预测从数据阵列快速访问数据。 高速缓存存储器包括多个存储器位置，多个存储位置被配置为存储路径预测，解码器，多个传输晶体管和读出放大器单元。 根据请求地址的第一部分来选择存储位置的子集。 解码器被配置为接收和解码所请求地址的第二部分。 地址的解码部分用于基于存储在所选择的存储位置子集内的预测方式来选择数据阵列的特定子集。 配置传输晶体管根据所请求地址的第三部分来选择数据阵列的第二子集。 然后，感测放大器单元从数据阵列内的第一子集和第二子集的相交处读取高速缓存行。

公开(公告)号：US06003128A

公开(公告)日：1999-12-14

申请号：US846656

申请日：1997-05-01

申请人： Thang M. Tran

发明人： Thang M. Tran

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/325 ,  G06F9/3844

摘要： An apparatus for prediction of loop instructions. Loop instructions decrement the value in a counter register and branch to a target address (specified by an instruction operand) if the decremented value of the counter register is greater than zero. The apparatus comprises a loop detection unit that detects the presence of a loop instruction in the instruction stream. An indication of the loop instruction is conveyed to a reorder buffer which stores speculative register values. If the apparatus is not currently processing the loop instruction, a compare value corresponding to the counter register prior to execution of the loop instruction is conveyed to a loop prediction unit. The loop prediction unit also increments a counter value upon receiving each indication of the loop instruction. This counter value is then compared to the compare value conveyed from the reorder buffer. If the counter value is one less than the compare value, a signal is asserted that indicates that the loop instruction should be predicted not-taken upon a next iteration of the loop. In this manner, loop prediction accuracy may be increased by correctly predicting the loop instruction not-taken. Because loops are commonly found in a variety of applications, increasing the accuracy of loop prediction, even slightly, may have a beneficial effect on performance. The loop operation is particularly important in scientific applications where it may be used to perform various digital signal processing routines and to traverse arrays.

摘要翻译： 一种用于预测循环指令的装置。 如果计数器寄存器的递减值大于零，则循环指令会递减计数器寄存器中的值并转移到目标地址（由指令操作数指定）。 该装置包括检测指令流中循环指令的存在的循环检测单元。 循环指令的指示被传送到存储推测寄存器值的重排序缓冲器。 如果设备当前没有处理循环指令，则在循环指令执行之前对应于计数器寄存器的比较值被传送到循环预测单元。 环路预测单元在接收到循环指令的每个指示时也增加计数器值。 然后将该计数器值与从重排序缓冲器传送的比较值进行比较。 如果计数器值比比较值小一个，则会产生一个信号，指示循环指令在循环的下一次迭代时不应被预测。 以这种方式，可以通过正确地预测不采用的循环指令来增加循环预测精度。 因为循环通常在各种应用中发现，所以即使稍微增加循环预测的准确性也可能对性能有有益的影响。 循环操作在可用于执行各种数字信号处理程序和遍历数组的科学应用中尤为重要。