公开(公告)号：US20240160069A1

公开(公告)日：2024-05-16

申请号：US18509920

申请日：2023-11-15

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Takuo KAITOH ,  Tomoyuki ITO ,  Yoshinori TANAKA

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/13357

CPC classification number: G02F1/136286 ,  G02F1/133365 ,  G02F1/133615

Abstract: A display device includes a wiring region including a gate wiring, a source wiring intersecting the gate wiring, and a first insulating layer between the gate wiring and the source wiring and an opening region including a pixel electrode on the first insulating layer and adjacent to the wiring region. The first insulating layer includes a first oxide insulating layer and a first nitride insulating layer, the first oxide insulating layer is disposed over the wiring region and the opening region, the first nitride insulating layer is disposed in the wiring region and includes a first opening overlapping the opening region, and the pixel electrode overlaps the first opening.

公开(公告)号：US20240069396A1

公开(公告)日：2024-02-29

申请号：US18457350

申请日：2023-08-29

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Hitoshi TANAKA

IPC: G02F1/1362

CPC classification number: G02F1/136222 ,  G02F1/136286

Abstract: According to one embodiment, a display device includes a transparent semiconductor, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a third insulating layer, a transparent electrode which is in contact with the semiconductor in a second contact hole penetrating the first insulating layer, the second insulating layer and the third insulating layer, a fourth insulating layer, a color filter, and a pixel electrode electrically connected to the transparent electrode. The first insulating layer and the second insulating layer are silicon oxide layers. At least one of the third insulating layer and the fourth insulating layer is a silicon nitride layer.

公开(公告)号：US20230017598A1

公开(公告)日：2023-01-19

申请号：US17862419

申请日：2022-07-12

Applicant: Japan Display Inc.

Inventor： Toshiki KANEKO ,  Akihiro HANADA

IPC: H01L29/786 ,  H01L29/417

Abstract: According to one embodiment, a semiconductor device includes a gate electrode, a first insulating layer covering the gate electrode, an oxide semiconductor provided on the first insulating layer immediately above the gate electrode, a source electrode in contact with the oxide semiconductor, and a drain electrode in contact with the oxide semiconductor. Each of the source electrode and the drain electrode includes an oxide conductive layer in contact with the oxide semiconductor, a first metal layer stacked on the oxide conductive layer, a second metal layer formed of a different material from the first metal layer and stacked on the first metal layer, and a third metal layer formed of a same material as the first metal layer and stacked on the second metal layer.

公开(公告)号：US20220367691A1

公开(公告)日：2022-11-17

申请号：US17660729

申请日：2022-04-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/426 ,  H01L29/786

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

公开(公告)号：US20220246764A1

公开(公告)日：2022-08-04

申请号：US17724512

申请日：2022-04-20

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  Tomoyuki ITO

IPC: H01L29/786

Abstract: The present invention addresses the problem of: realizing a TFT that uses an oxide semiconductor and that is capable of maintaining stable characteristics even in the case where the TFT is miniaturized; and realizing a display device that has high-definition pixels using such a TFT. To solve this problem, the present invention has the following configuration. A semiconductor device including an oxide semiconductor TFT formed using an oxide semiconductor film 109, the semiconductor device being characterized in that: the channel length of the oxide semiconductor TFT is 1.3 to 2.3 μm; and the sheet resistance of a source region 1092 and a drain region 1091 of the oxide semiconductor film 109 is 1.4 to 20 KΩ/□.

公开(公告)号：US20220238558A1

公开(公告)日：2022-07-28

申请号：US17583231

申请日：2022-01-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Akihiro HANADA

IPC: H01L27/12 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a polycrystalline silicon semiconductor, an oxide semiconductor, a gate electrode located directly above the oxide semiconductor, a first conductive layer in contact with the polycrystalline silicon semiconductor via a first contact hole, and in contact with the oxide semiconductor via a second contact hole and a second conductive layer stacked on the first conductive layer between the first contact hole and the second contact hole. The first conductive layer includes an extending portion extending from the second contact hole toward the gate electrode. The second conductive layer is not stacked on the extending portion. The first conductive layer is thinner than the second conductive layer.

公开(公告)号：US20220190164A1

公开(公告)日：2022-06-16

申请号：US17549882

申请日：2021-12-14

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Toshinari SASAKI ,  Takeshi SAKAI ,  Akihiro HANADA ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.

公开(公告)号：US20220165826A1

公开(公告)日：2022-05-26

申请号：US17533127

申请日：2021-11-23

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L27/32 ,  H01L51/56

Abstract: According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region.

公开(公告)号：US20220140117A1

公开(公告)日：2022-05-05

申请号：US17511633

申请日：2021-10-27

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Takuo KAITOH ,  Ryo ONODERA ,  Takashi OKADA ,  Tomoyuki ITO ,  Toshiki KANEKO

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/385

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film.

公开(公告)号：US20210134848A1

公开(公告)日：2021-05-06

申请号：US17148653

申请日：2021-01-14

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Toshihide JINNAI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66

Abstract: An object of the present invention is to provide a technology using which, in a thin film transistor using oxide semiconductor, the resistance of a channel region of the oxide semiconductor is made high, and at the same time the resistances of a source region and a drain region of the oxide semiconductor are made low. There is provided a semiconductor device including: a thin film transistor including oxide semiconductor, the oxide semiconductor including a channel region, a drain region, and a source region; a gate insulating film formed on the channel region; an aluminum oxide film formed on the gate insulating film; and a gate electrode formed on the aluminum oxide film, wherein the aluminum oxide film has a region that covers neither the drain region nor the source region in a plane view.