公开(公告)号：US20240402552A1

公开(公告)日：2024-12-05

申请号：US18798914

申请日：2024-08-09

Applicant: Japan Display Inc.

Inventor： Toshihide JINNAI ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  lsao SUZUMURA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786 ,  H10K59/131

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor is covered by a first insulating film, a first drain electrode is connected to the oxide semiconductor via a first through hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor via second through hole formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode and the first source electrode, a drain wiring connects to the first drain electrode via a third through hole formed in the second insulating film, a source wiring is connected to the first source electrode via a fourth through hole formed in the second insulating film.

公开(公告)号：US20240379865A1

公开(公告)日：2024-11-14

申请号：US18651909

申请日：2024-05-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/417

Abstract: A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.

公开(公告)号：US20240332427A1

公开(公告)日：2024-10-03

申请号：US18604840

申请日：2024-03-14

Applicant: Japan Display Inc.

Inventor： Marina MOCHIZUKI ,  Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/6675

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.

公开(公告)号：US20240312999A1

公开(公告)日：2024-09-19

申请号：US18588249

申请日：2024-02-27

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1251

Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.

公开(公告)号：US20240178325A1

公开(公告)日：2024-05-30

申请号：US18519392

申请日：2023-11-27

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/7869 ,  H01L29/0603 ,  H01L29/78696

Abstract: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm−3.

公开(公告)号：US20230068478A1

公开(公告)日：2023-03-02

申请号：US17894176

申请日：2022-08-24

Applicant: Japan Display Inc.

Inventor： Ryo ONODERA ,  Masashi TSUBUKU ,  Hajime WATAKABE

IPC: H01L29/786

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first insulating layer disposed on the substrate, an oxide semiconductor disposed on the first insulating layer and formed in an island shape, a second insulating layer covering the oxide semiconductor, a gate electrode disposed on the second insulating layer, and a source electrode and a drain electrode in contact with the oxide semiconductor. The oxide semiconductor includes a plurality of first openings located between the gate electrode and the source electrode, and a plurality of second openings located between the gate electrode and the drain electrode, in planar view.

公开(公告)号：US20210257402A1

公开(公告)日：2021-08-19

申请号：US17167081

申请日：2021-02-04

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Akihiro HANADA ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Fumiya KIMURA ,  Isao SUZUMURA

IPC: H01L27/146

Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.

公开(公告)号：US20240332428A1

公开(公告)日：2024-10-03

申请号：US18617858

申请日：2024-03-27

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1248 ,  H01L29/42384

Abstract: A semiconductor device comprises a first insulating layer; a metal oxide layer mainly composed of aluminum on the first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; and a second insulating layer on the gate electrode. The metal oxide layer and the oxide semiconductor layer are both patterned, and the oxide semiconductor layer has a first region in contact with the gate insulating layer and a second region continuous with the first region in a first direction and in contact with the gate insulating layer and the second insulating layer.

公开(公告)号：US20240290861A1

公开(公告)日：2024-08-29

申请号：US18435094

申请日：2024-02-07

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device according to an embodiment includes: a first gate electrode; a first insulating layer on the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen. A thickness of the first layer is 10 nm or more and 190 nm or less. A thickness of the second layer is 10 nm or more and 100 nm or less. A total thickness of the first layer and the second layer is 200 nm or less. A thickness of the third layer 1 nm or more and 10 nm or less.

公开(公告)号：US20240088192A1

公开(公告)日：2024-03-14

申请号：US18515288

申请日：2023-11-21

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Akihiro HANADA ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Fumiya KIMURA ,  Isao SUZUMURA

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/14636 ,  H01L27/14689

Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.