公开(公告)号：US20250120243A1

公开(公告)日：2025-04-10

申请号：US18985529

申请日：2024-12-18

Applicant: Japan Display Inc.

Inventor： Marina MOCHIZUKI ,  Isao SUZUMURA

IPC: H10K30/65 ,  H10K30/82

Abstract: The purpose of the present invention is to prevent a decrease in light reflection characteristic and an increase in electric resistance due to oxidation of silver in a semiconductor device including an optical sensor in which silver is used for an anode of a photoconductive film. The present invention has a following structure to solve the problem: A semiconductor device includes a thin film transistor formed on a substrate 100. An electrode connected electrically to the thin film transistor is formed of a silver film 128. A first indium tin oxide (ITO) film 129 is formed on the silver film 128. An alumina (AlOx) film 130 is formed on the first ITO film 129.

公开(公告)号：US20240069400A1

公开(公告)日：2024-02-29

申请号：US18503351

申请日：2023-11-07

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Toshihide JINNAI ,  Isao SUZUMURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  H10K50/86 ,  H10K59/131

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136277 ,  G02F1/136286 ,  H01L29/78633 ,  H01L29/78672 ,  H10K50/865 ,  H10K59/131

Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

公开(公告)号：US20230387146A1

公开(公告)日：2023-11-30

申请号：US18366859

申请日：2023-08-08

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Isao SUZUMURA ,  Akihiro HANADA ,  Yohei YAMAGUCHI

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1292 ,  H01L29/24 ,  H01L29/78666 ,  H01L29/7869 ,  H01L29/66969 ,  H01L27/1225 ,  H01L29/66757

Abstract: A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.

公开(公告)号：US20230284509A1

公开(公告)日：2023-09-07

申请号：US18175549

申请日：2023-02-28

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Fumiya KIMURA ,  Hiroshi OGAWA

IPC: H10K59/80 ,  H10K71/20

CPC classification number: H10K59/80524 ,  H10K59/871 ,  H10K71/231 ,  H10K2102/103

Abstract: According to one embodiment, a display device manufacturing method comprises forming a lower electrode including a first metal layer and a conductive oxide layer which covers the first metal layer and which has a thickness of 15 nm or more and 50 nm or less, forming a rib covering at least a part of the lower electrode and including a pixel aperture which exposes the conductive oxide layer, forming a second metal layer above the rib and the conductive oxide layer exposed through the pixel aperture, and patterning the second metal layer by etching including wet etching to form a partition on the rib.

公开(公告)号：US20200152668A1

公开(公告)日：2020-05-14

申请号：US16743080

申请日：2020-01-15

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Kazufumi WATABE ,  Yoshinori ISHII ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  G02F1/1362 ,  G02F1/133 ,  G02F1/1368 ,  H01L29/786 ,  H01L29/24 ,  H01L29/51

Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.

公开(公告)号：US20190250443A1

公开(公告)日：2019-08-15

申请号：US16395491

申请日：2019-04-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Isao SUZUMURA ,  Hirokazu WATANABE ,  Akihiro HANADA

IPC: G02F1/1368 ,  H01L27/12 ,  H01L51/50 ,  H01L21/8234 ,  H01L29/786

Abstract: A display device comprising: a first TFT using silicon (Si) and a second TFT using oxide semiconductor are formed on a substrate, a distance between the silicon (Si) and the substrate is smaller than a distance between the oxide semiconductor and the substrate, a drain source electrode of the first TFT connects with the silicon (Si) via a first through hole, a drain source electrode of the second TFT connects with the oxide semiconductor via a second through hole, metal films are made on the oxide semiconductor sandwiching a channel of the oxide semiconductor in a plan view, the channel has a channel width, an ALO layer is formed on the metal films and the oxide semiconductor, the second source drain electrode and the metal films are connected via the second through hole formed in the AlO layer.

公开(公告)号：US20180076239A1

公开(公告)日：2018-03-15

申请号：US15678501

申请日：2017-08-16

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Hajime Watakabe ,  Akihiro Hanada ,  Hirokazu Watanabe

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L27/1251 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02675 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/127 ,  H01L27/1274 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/78693 ,  H01L2227/323

Abstract: The purpose of the present invention is to form both LTPS TFT and Ply-Si TFT on a same substrate. The feature of the display device to realize the above purpose is that: a display device comprising: a substrate including a first TFT having an oxide semiconductor layer and a second TFT having a Poly-Si layer, an undercoat is formed on the substrate, the oxide semiconductor layer is formed on or above the undercoat, a first interlayer insulating film is formed on or above the oxide semiconductor layer, the Poly-Si layer is formed on or above the first interlayer insulating film.

公开(公告)号：US20170054028A1

公开(公告)日：2017-02-23

申请号：US15230915

申请日：2016-08-08

Applicant: Japan Display Inc.

Inventor： Toshinari SASAKI ,  Isao SUZUMURA

IPC: H01L29/786 ,  H01L29/40 ,  H01L21/4757 ,  H01L21/465 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L29/401 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor device includes an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first barrier layer below the oxide semiconductor layer, and a second barrier layer above the oxide semiconductor layer, the second barrier layer covering a top surface and side surfaces of the oxide semiconductor layer and being in contact with the first barrier layer in a region around the oxide semiconductor layer.

Abstract translation: 半导体器件包括氧化物半导体层，面对氧化物半导体层的栅极电极，氧化物半导体层和栅电极之间的栅极绝缘层，氧化物半导体层下面的第一势垒层和氧化物上方的第二势垒层 半导体层，所述第二阻挡层覆盖所述氧化物半导体层的顶表面和侧表面，并且在所述氧化物半导体层周围的区域中与所述第一阻挡层接触。

公开(公告)号：US20160284867A1

公开(公告)日：2016-09-29

申请号：US15172576

申请日：2016-06-03

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L29/786 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1343 ,  H01L29/24 ,  G02F1/1333

CPC classification number: H01L29/78696 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/133357 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: In a bottom gate thin film transistor using a first oxide semiconductor layer as a channel layer, the first oxide semiconductor layer and second semiconductor layers include In and O. An (O/In) ratio of the second oxide semiconductor layers is equal to or larger than that of the first oxide semiconductor layer, and a film thickness thereof is thicker than that of the first oxide semiconductor layer.

Abstract translation: 在使用第一氧化物半导体层作为沟道层的底栅极薄膜晶体管中，第一氧化物半导体层和第二半导体层包括In和O.第二氧化物半导体层的（O / In）比等于或大于 比第一氧化物半导体层的厚度厚，其厚度比第一氧化物半导体层厚。

公开(公告)号：US20140054583A1

公开(公告)日：2014-02-27

申请号：US13965418

申请日：2013-08-13

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Isao SUZUMURA

IPC: H01L33/00

CPC classification number: H01L33/0041 ,  H01L21/77 ,  H01L27/1225 ,  H01L29/7869

Abstract: A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode.

Abstract translation: 栅极绝缘膜具有符合栅电极的表面形状的凸部和沿着栅电极的表面从栅电极的周边高度变化的台阶部。 在栅极绝缘膜上设置氧化物半导体层，以具有沟道区域，源极区域和漏极区域的晶体管构成区域，并且与晶体管构成区域分离的覆盖区域和 覆盖栅极绝缘膜的台阶部分。 沟道保护层设置在氧化物半导体层的沟道区上。 源极电极和漏电极分别与氧化物半导体层的源极区域和漏极区域接触。 钝化层设置在源电极和漏电极上。