公开(公告)号：US07752589B2

公开(公告)日：2010-07-06

申请号：US11620059

申请日：2007-01-05

申请人： Robert J. Allen ,  Sarah C. Braasch ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Kevin W. McCullen ,  Evanthia Papadopoulou ,  Mervyn Y. Tan ,  Robert F. Walker

发明人： Robert J. Allen ,  Sarah C. Braasch ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Kevin W. McCullen ,  Evanthia Papadopoulou ,  Mervyn Y. Tan ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.

摘要翻译： 一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

公开(公告)号：US07657859B2

公开(公告)日：2010-02-02

申请号：US11275076

申请日：2005-12-08

申请人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

发明人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

摘要翻译： 公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。 该方法执行满足布线拥塞约束的初始全局路由。 接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。 之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。 使用关键区域产量模型进行布线后布线宽度和布线调整。 此外，该方法允许优化已经路由的数据。

公开(公告)号：US20090064061A1

公开(公告)日：2009-03-05

申请号：US11846017

申请日：2007-08-28

申请人： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

发明人： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

摘要翻译： 包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。 该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。 然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。 该方法可以基于与参数相关的约束来可选地调整物理设计形状。

公开(公告)号：US07490308B2

公开(公告)日：2009-02-10

申请号：US11278162

申请日：2006-03-31

申请人： Christopher J. Gonzalez ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen I. Runyon ,  Xiaoyun K. Wu

发明人： Christopher J. Gonzalez ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen I. Runyon ,  Xiaoyun K. Wu

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/08

摘要： A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

摘要翻译： 修改用于性能优化的VLSI布局的方法包括为要修改的多个原始设备形状定义修改的基本规则集，并将多个原始设备形状平坦化为主单元。 基于经修改的基础规则集，对平坦化的设备形状执行布局优化操作，以便创建多个修改的设备形状。 然后从修改的设备形状和原始设备形状之间的差异创建覆盖单元。

公开(公告)号：US07454721B2

公开(公告)日：2008-11-18

申请号：US11276374

申请日：2006-02-27

申请人： Jason D. Hibbeler ,  Rani Narayan ,  Robert F. Walker

发明人： Jason D. Hibbeler ,  Rani Narayan ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact they have on the yield of the integrated circuit design. The layout is optimized according to the prioritized base ground rules and recommended ground rules.

摘要翻译： 一种用于优化集成电路设计布局的方法，装置和计算机程序产品。 根据其对集成电路设计的收益的影响，将基础规则和建议的基本规则放在首位。 布局根据优先的基础规则和推荐的基本规则进行优化。

公开(公告)号：US07337415B2

公开(公告)日：2008-02-26

申请号：US10711978

申请日：2004-10-18

申请人： Paul H. Bergeron ,  Jason D. Hibbeler ,  Gustavo E. Tellez

发明人： Paul H. Bergeron ,  Jason D. Hibbeler ,  Gustavo E. Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

摘要翻译： 提供三维结构，其提高半导体器件中某些结构的制造成品率。 三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。 因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。 提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

公开(公告)号：US07120887B2

公开(公告)日：2006-10-10

申请号：US10707845

申请日：2004-01-16

申请人： Henry A. Bonges, III ,  Michael S. Gray ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker

发明人： Henry A. Bonges, III ,  Michael S. Gray ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

摘要翻译： 用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。 本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。 联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

公开(公告)号：US07093234B2

公开(公告)日：2006-08-15

申请号：US09939005

申请日：2001-08-24

申请人： Jason D. Hibbeler ,  Jhy-Chun Wang

发明人： Jason D. Hibbeler ,  Jhy-Chun Wang

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F11/3466 ,  G06F11/3423 ,  G06F2201/865

摘要： A method, and computer readable medium for the dynamic CPU (Central Processing Unit) usage and function call tracing on a target application. The setup of the tracing uses a -pg like solution, and is implemented using the DPCL (Dynamic Probe Class Library). The output is presented in a gmon.out format, which allows the use of popular analysis tools. The program being traced need not be recompiled or re-linked. This is particularly important if the source code is not available. The dynamic feature allows for different choices of profiling and the choice can even be changed once the target application is running.

公开(公告)号：US07761821B2

公开(公告)日：2010-07-20

申请号：US11837732

申请日：2007-08-13

申请人： Robert J. Allen ,  Cam V. Endicott ,  Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani Narayan ,  Robert F. Walker ,  Xin Yuan

发明人： Robert J. Allen ,  Cam V. Endicott ,  Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani Narayan ,  Robert F. Walker ,  Xin Yuan

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5077 ,  G06F17/5068

摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.

摘要翻译： 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

公开(公告)号：US20100023913A1

公开(公告)日：2010-01-28

申请号：US12572297

申请日：2009-10-02

申请人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

发明人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

摘要翻译： 公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。 该方法执行满足布线拥塞约束的初始全局路由。 接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。 之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。 使用关键区域产量模型进行布线后布线宽度和布线调整。 此外，该方法允许优化已经路由的数据。