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31 条记录 (耗时 0.037 秒)

    Cloned and original circuit shape merging
    1.
    发明授权
    Cloned and original circuit shape merging 失效
    克隆和原始电路形状合并

    公开(公告)号：US07120887B2

    公开(公告)日：2006-10-10

    申请号：US10707845

    申请日：2004-01-16

    申请人： Henry A. Bonges, III ,  Michael S. Gray ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker

    发明人： Henry A. Bonges, III ,  Michael S. Gray ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

    摘要翻译： 用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。 本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。 联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

    Context aware sub-circuit layout modification
    2.
    发明授权
    Context aware sub-circuit layout modification 失效
    上下文感知子电路布局修改

    公开(公告)号：US07735042B2

    公开(公告)日：2010-06-08

    申请号：US11831998

    申请日：2007-08-01

    申请人： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    发明人： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.

    摘要翻译： 公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。 该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

    CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION
    3.
    发明申请
    CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION 失效
    背景知识子电路布局修改

    公开(公告)号：US20090037851A1

    公开(公告)日：2009-02-05

    申请号：US11831998

    申请日：2007-08-01

    申请人： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    发明人： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.

    摘要翻译： 公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。 该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

    Integrated circuit selective scaling
    5.
    发明授权
    Integrated circuit selective scaling 有权
    集成电路选择性缩放

    公开(公告)号：US07363601B2

    公开(公告)日：2008-04-22

    申请号：US10711959

    申请日：2004-10-15

    申请人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    发明人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

    摘要翻译： 公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。