公开(公告)号：US20090315099A1

公开(公告)日：2009-12-24

申请号：US12367988

申请日：2009-02-09

申请人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

发明人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

IPC分类号： H01L25/07 ,  H01L21/76

CPC分类号： H01L27/11573 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11592 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

摘要翻译： 集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。 集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。 隧道势垒层可以包括HVT的栅极电介质的一部分。 隧道势垒层可以构成HVT的整个栅电介质。 相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。 因此，可以提高驱动器芯片IC的制造效率。

公开(公告)号：US20090212340A1

公开(公告)日：2009-08-27

申请号：US12392656

申请日：2009-02-25

申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/11521

摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.

摘要翻译： 一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸 其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

公开(公告)号：US20090001451A1

公开(公告)日：2009-01-01

申请号：US12146653

申请日：2008-06-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

公开(公告)号：US20080105918A1

公开(公告)日：2008-05-08

申请号：US11709816

申请日：2007-02-23

申请人： Sang-Hun Jeon ,  Chang-Seok Kang ,  Jung-Dal Choi ,  Jin-Taek Park ,  Woong-Hee Sohn ,  Won-Seok Jung

发明人： Sang-Hun Jeon ,  Chang-Seok Kang ,  Jung-Dal Choi ,  Jin-Taek Park ,  Woong-Hee Sohn ,  Won-Seok Jung

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/78

摘要： A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.

摘要翻译： 非易失性存储器件包括：包括单元区域和外围电路区域的半导体衬底，单元区域上的单元栅极和外围电路区域上的外围电路栅极，其中，所述单元栅极包括半导体上的电荷存储绝缘层 基板，电荷存储绝缘层上的栅极电极和栅电极上的导电层，外围电路栅极包括在半导体基板上的栅极绝缘层，栅极绝缘层上的半导体层， 半导体层和欧姆层上的导电层。

公开(公告)号：US20050250307A1

公开(公告)日：2005-11-10

申请号：US11022240

申请日：2004-12-22

申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。