公开(公告)号：US20090199020A1

公开(公告)日：2009-08-06

申请号：US12023536

申请日：2008-01-31

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.

摘要翻译： 提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。 小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。 小巧包括处理器核心和相关联的存储器高速缓存。 功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。 电源管理控制微架构根据功率设置设置微体系结构电源管理技术。 全球电源管理控制器发出第一个命令。 全局功率管理控制器可以驻留在微处理器上或者关闭。 全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。 每个小穗可以设置为分开的功率水平。

公开(公告)号：US07453816B2

公开(公告)日：2008-11-18

申请号：US11054288

申请日：2005-02-09

申请人： James Stephen Fields, Jr. ,  Michael Stephen Floyd ,  Benjiman Lee Goodman ,  Paul Frank Lecocq ,  Praveen S. Reddy

发明人： James Stephen Fields, Jr. ,  Michael Stephen Floyd ,  Benjiman Lee Goodman ,  Paul Frank Lecocq ,  Praveen S. Reddy

IPC分类号： G01R31/08 ,  G06F13/00

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed.If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20080134180A1

公开(公告)日：2008-06-05

申请号：US11960878

申请日：2007-12-20

申请人： Michael Stephen Floyd

发明人： Michael Stephen Floyd

IPC分类号： G06F9/46

CPC分类号： G06F9/3009 ,  G06F9/3851 ,  G06F9/5027 ,  G06F2209/5018

摘要： A processor supporting thread-execution-state-sensitive supervisory commands provides a mechanism for executing supervisory commands for live threads. The commands may be sent from a service processor or another primary processor in the system or may be supplied by the processor itself through supervisory software control. Since the state of execution of one or more threads may change dynamically within a processor core, an external processor will not know the thread execution state at the time the command operates. The method and apparatus provide a command set and logic that supports selective execution of particular commands directed at “alive” threads (or threads in some other determinable execution state), whereby the command is performed only on resources and/or execution units depending on the actual state of thread execution when the command operates within the processor.

摘要翻译： 支持线程执行状态敏感的监控命令的处理器提供了一种用于执行活动线程的监控命令的机制。 命令可以从系统中的服务处理器或另一主处理器发送，或者可以由处理器本身通过监控软件控制来提供。 由于一个或多个线程的执行状态可能在处理器核心内动态地改变，所以外部处理器将不知道命令操作时的线程执行状态。 该方法和装置提供一种命令集和逻辑，该命令集和逻辑支持选择性执行指向“活着”线程的特定命令（或某些其他可确定的执行状态的线程），由此该命令仅在资源和/或执行单元上执行，这取决于 当命令在处理器内运行时线程执行的实际状态。

公开(公告)号：US07305639B2

公开(公告)日：2007-12-04

申请号：US11055863

申请日：2005-02-11

申请人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

发明人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

摘要翻译： 提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。 提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。 然后提供第一验证机制以验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。 提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。 提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。

公开(公告)号：US07213169B2

公开(公告)日：2007-05-01

申请号：US10406650

申请日：2003-04-03

申请人： John Steven Dodson ,  Michael Stephen Floyd ,  Jerry Don Lewis ,  Gary Alan Morrison

发明人： John Steven Dodson ,  Michael Stephen Floyd ,  Jerry Don Lewis ,  Gary Alan Morrison

IPC分类号： G06F11/00

CPC分类号： G06F11/364

摘要： An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written. The time stamp trace record includes a count of the number of address transactions that were not converted to trace records.

摘要翻译： 公开了一种用于在分布式存储器对称多处理器系统中执行不精确总线跟踪的装置。 该装置包括总线跟踪宏（BTM）模块，其可以控制数据处理系统中的一个或多个存储器控制器所看到的窥探流量，并利用连接到存储器控制器的本地存储器来存储跟踪记录。 在BTM模块启用跟踪操作之后，BTM模块会窥探互连上的事务，并将包含在这些事务中的信息打包成与存储器控制器中写入缓冲区匹配的大小的数据块。 此外，BTM模块还包括一个丢弃的记录计数器，用于计数未转换为跟踪记录的地址事务数，因为所有的写入缓冲区已经完全满载。 写入缓冲区满满后，插入新的跟踪记录之前插入时间戳跟踪记录。 时间戳跟踪记录包括未转换为跟踪记录的地址事务数的计数。

公开(公告)号：US07089462B2

公开(公告)日：2006-08-08

申请号：US10418499

申请日：2003-04-17

申请人： Michael Stephen Floyd ,  Kevin Franklin Reick

发明人： Michael Stephen Floyd ,  Kevin Franklin Reick

IPC分类号： G06F11/00 ,  G06F11/30

CPC分类号： G06F11/1604 ,  G06F11/1608

摘要： An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.

摘要翻译： 用于检测多处理系统中的时钟故障的早期时钟故障检测方法和电路提供了可以用于关闭多处理系统或处理器的错误系统，所述错误系统或处理器在由多个处理器之间的同步丢失引起的错误可能从处理器传播导致存储或 其他系统被破坏。 检测电路对通过乘以外部主时钟信号而产生的高频内部处理器时钟的周期进行计数，并且检测在外部主时钟信号的转换之间是否经过了预定数量的时钟周期。 检测电路在小于主时钟周期内提供时钟故障输出，可用于关闭处理器，处理器之间的系统或互连，防止在高频时钟漂移足够导致错误之前丢失或损坏数据 。

公开(公告)号：US06802031B2

公开(公告)日：2004-10-05

申请号：US09864114

申请日：2001-05-24

申请人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick

发明人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick

IPC分类号： G06F1100

CPC分类号： G06F11/366 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/835 ,  G06F2201/86 ,  G06F2201/88

摘要： A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

摘要翻译： 用于记录信号状态的迹线阵列包括用于k个跟踪信号的N个存储位置。 在写模式下，地址生成器将事件信号计数器和周期时钟计数器的输出相结合，生成跟踪数组地址。 每次发生事件信号时写入起始码，并保存事件地址。 通过停止信号停止录像，并保存停止地址。 当在周期时钟时间的任何跟踪信号中没有状态变化时，压缩码和时间戳码被写入，以压缩记录的跟踪信号数据。 输出处理器读出跟踪信号的存储状态，并使用起始码，事件地址，停止地址，压缩码和时间戳重建原始跟踪信号序列进行分析。

公开(公告)号：US06745321B1

公开(公告)日：2004-06-01

申请号：US09436104

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  Kevin Franklin Reick

发明人： Michael Stephen Floyd ,  Kevin Franklin Reick

IPC分类号： G06F1122

CPC分类号： G06F11/0721 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861 ,  G06F11/079

摘要： A method and apparatus for harvesting problematic code sections that may cause a hang condition based on a hardware design flaw is presented. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, steps are employed by hardware and/or software to recover from a hang condition, such as flushing instructions dispatched to the plurality of execution units. Upon successful completion of hang recovery, a debug interrupt is injected, causing a debug interrupt handler to be immediately involved before the resumption of normal execution. The debug interrupt handler may then harvest problematic code sections in the undisturbed execution error that may have caused the hang condition.

摘要翻译： 提出了一种用于收集可能导致基于硬件设计缺陷的挂起状况的有问题的代码段的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，硬件和/或软件采用步骤从挂起状态恢复，诸如分配给多个执行单元的刷新指令。 在成功完成挂起恢复后，将注入调试中断，导致在恢复正常执行之前立即执行调试中断处理程序。 调试中断处理程序可能会收到可能导致挂起状况的未受干扰的执行错误中的有问题的代码段。

公开(公告)号：US06543003B1

公开(公告)日：2003-04-01

申请号：US09436106

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

IPC分类号： G06F1100

CPC分类号： G06F9/3885 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/1405

摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.

摘要翻译： 一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，分配给多个执行单元的指令被刷新。

公开(公告)号：US08001394B2

公开(公告)日：2011-08-16

申请号：US12023536

申请日：2008-01-31

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.

摘要翻译： 提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。 小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。 小巧包括处理器核心和相关联的存储器高速缓存。 功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。 电源管理控制微架构根据功率设置设置微体系结构电源管理技术。 全球电源管理控制器发出第一个命令。 全局功率管理控制器可以驻留在微处理器上或者关闭。 全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。 每个小穗可以设置为分开的功率水平。