公开(公告)号：US06868034B2

公开(公告)日：2005-03-15

申请号：US10639858

申请日：2003-08-13

申请人： One-Gyun La ,  Yun-Sang Lee

发明人： One-Gyun La ,  Yun-Sang Lee

IPC分类号： G11C8/08 ,  G11C7/10 ,  G11C8/14 ,  G11C11/408 ,  G11C29/28 ,  G11C8/00

CPC分类号： G11C29/28 ,  G11C7/1021 ,  G11C7/1045 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2029/1202 ,  G11C2029/1804

摘要： A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

摘要翻译： 一种具有允许用户改变半导体器件的寻址长度的架构的半导体存储器件。 用于改变半导体器件的页面长度的电路和方法使得能够选择性地激活存储器单元阵列的存储器单元阵列块的一个或多个对应字线（具有相同行地址），从而根据指定的操作模式改变页长度 。

公开(公告)号：US06459636B2

公开(公告)日：2002-10-01

申请号：US09838358

申请日：2001-04-19

申请人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

发明人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.

公开(公告)号：US06438047B1

公开(公告)日：2002-08-20

申请号：US09908192

申请日：2001-07-18

申请人： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

发明人： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

IPC分类号： G11C700

CPC分类号： G11C29/846

摘要： A semiconductor memory device comprises a memory cell array, at least one redundant cell control, a sense amplifier, and at least one redundant cell. The memory cell array receives and outputs data through data I/O line groups. The redundant cell control stores a defective cell address, generates a redundant cell enable control signal when the defective cell address is equal to an input cell address, generates a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generates a redundant cell write control signal during a write operation in response to the redundant cell enable control signal. The sense amplifier is connected to an I/O line group commonly connected to the data I/O line groups, amplifies and outputs data outputted from the memory cell array during the read operation, and is disabled in response to the redundant cell read control signal. The redundant cell stores input data transferred to the I/O line group in response to the redundant cell write control signal and outputs stored data in response to the redundant cell read control signal.

摘要翻译： 半导体存储器件包括存储单元阵列，至少一个冗余单元控制，读出放大器和至少一个冗余单元。 存储单元阵列通过数据I / O线组接收和输出数据。 冗余单元控制存储故障单元地址，当缺陷单元地址等于输入单元地址时产生冗余单元使能控制信号，在读操作期间响应冗余单元使能控制信号产生冗余单元读控制信号 并且响应于冗余单元使能控制信号在写操作期间产生冗余单元写入控制信号。 感测放大器连接到通常连接到数据I / O线组的I / O线组，在读操作期间放大并输出从存储单元阵列输出的数据，并响应于冗余单元读取控制信号而被禁止 。 冗余单元响应于冗余单元写入控制信号存储传送到I / O线组的输入数据，并根据冗余单元读取控制信号输出存储的数据。

公开(公告)号：US06392938B1

公开(公告)日：2002-05-21

申请号：US09955635

申请日：2001-09-19

申请人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

发明人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

IPC分类号： G11C700

CPC分类号： G11C29/785

摘要： A semiconductor memory device comprises a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation. The mode control signal setting means sets a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.

摘要翻译： 半导体存储器件包括存储单元阵列，缺陷地址编程装置，冗余使能信号发生装置，输出装置和模式控制信号设置装置。 存储单元阵列包括多个存储单元。 缺陷地址编程装置响应于从外部施加的第一控制信号和地址信号，以封装级别编程多个存储器单元中的有缺陷的存储单元的冗余控制信号和缺陷地址。 当地址与缺陷地址一致时，冗余使能信号发生装置响应于冗余控制信号产生比较重合信号。 输出装置在测试操作期间响应于第二控制信号将比较重合信号输出到外部部分。 模式控制信号设置装置响应于从外部施加的命令信号和模式设置信号来设置第一和第二控制信号的状态。

公开(公告)号：US06345011B2

公开(公告)日：2002-02-05

申请号：US09758526

申请日：2001-01-10

申请人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

发明人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

IPC分类号： G11C800

CPC分类号： G11C7/10

摘要： A semiconductor memory device including a plurality of memory blocks having associated with one or more circuit blocks therearound, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between the adjacent memory blocks while first portions of the input/output lines of the second group are arranged within the circuit blocks around the adjacent memory blocks. Second portions of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks.

摘要翻译： 公开了一种包括与其周围的一个或多个电路块相关联的多个存储块的半导体存储器件，以及与存储器块相关联的多个输入/输出线。 输入/输出线分成至少第一组和第二组。 第一组的输入/输出线的第一部分被布置在相邻的存储块之间，而第二组的输入/输出线的第一部分被布置在邻近的存储块周围的电路块内。 第一组的输入/输出线的第二部分布置在存储块周围的电路块上，而第二组的输入/输出线的第二部分被布置在相邻的存储块之间。