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180 条记录 (耗时 0.025 秒)

    Mode selection circuit for semiconductor memory device
    2.
    发明授权
    Mode selection circuit for semiconductor memory device 有权

    公开(公告)号：US06459636B2

    公开(公告)日：2002-10-01

    申请号：US09838358

    申请日：2001-04-19

    申请人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

    发明人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

    IPC分类号： G11C700

    CPC分类号： G11C29/46

    摘要： A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.

    Semiconductor memory device and method of identifying programmed defective address thereof
    3.
    发明授权
    Semiconductor memory device and method of identifying programmed defective address thereof 有权
    半导体存储器件及识别编程的缺陷地址的方法

    公开(公告)号：US06392938B1

    公开(公告)日：2002-05-21

    申请号：US09955635

    申请日：2001-09-19

    申请人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

    发明人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

    IPC分类号： G11C700

    CPC分类号： G11C29/785

    摘要： A semiconductor memory device comprises a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation. The mode control signal setting means sets a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.

    摘要翻译： 半导体存储器件包括存储单元阵列，缺陷地址编程装置，冗余使能信号发生装置，输出装置和模式控制信号设置装置。 存储单元阵列包括多个存储单元。 缺陷地址编程装置响应于从外部施加的第一控制信号和地址信号，以封装级别编程多个存储器单元中的有缺陷的存储单元的冗余控制信号和缺陷地址。 当地址与缺陷地址一致时，冗余使能信号发生装置响应于冗余控制信号产生比较重合信号。 输出装置在测试操作期间响应于第二控制信号将比较重合信号输出到外部部分。 模式控制信号设置装置响应于从外部施加的命令信号和模式设置信号来设置第一和第二控制信号的状态。

    Input/output line structure of a semiconductor memory device
    4.
    发明授权
    Input/output line structure of a semiconductor memory device 有权
    半导体存储器件的输入/输出线结构

    公开(公告)号：US06345011B2

    公开(公告)日：2002-02-05

    申请号：US09758526

    申请日：2001-01-10

    申请人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

    发明人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

    IPC分类号： G11C800

    CPC分类号： G11C7/10

    摘要： A semiconductor memory device including a plurality of memory blocks having associated with one or more circuit blocks therearound, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between the adjacent memory blocks while first portions of the input/output lines of the second group are arranged within the circuit blocks around the adjacent memory blocks. Second portions of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks.

    摘要翻译： 公开了一种包括与其周围的一个或多个电路块相关联的多个存储块的半导体存储器件，以及与存储器块相关联的多个输入/输出线。 输入/输出线分成至少第一组和第二组。 第一组的输入/输出线的第一部分被布置在相邻的存储块之间，而第二组的输入/输出线的第一部分被布置在邻近的存储块周围的电路块内。 第一组的输入/输出线的第二部分布置在存储块周围的电路块上，而第二组的输入/输出线的第二部分被布置在相邻的存储块之间。

    SEMICONDUCTOR MEMORY DEVICES INCLUDING BURN-IN TEST CIRCUITS
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES INCLUDING BURN-IN TEST CIRCUITS 有权
    包含烧录电路的半导体存储器件

    公开(公告)号：US20100246300A1

    公开(公告)日：2010-09-30

    申请号：US12731749

    申请日：2010-03-25

    申请人： Jong-Hyun Choi ,  Sang-Seok Kang

    发明人： Jong-Hyun Choi ,  Sang-Seok Kang

    IPC分类号： G11C29/00 ,  G11C7/12

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

    摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

    摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。 控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。 第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。 还讨论了相关的操作方法。

    Decoding circuit for controlling activation of wordlines in a semiconductor memory device
    6.
    发明授权
    Decoding circuit for controlling activation of wordlines in a semiconductor memory device 失效
    用于控制半导体存储器件中的字线激活的解码电路

    公开(公告)号：US06490222B2

    公开(公告)日：2002-12-03

    申请号：US09875371

    申请日：2001-06-05

    申请人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Jei-Hwan Yoo ,  Jae-Hoon Joo

    发明人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Jei-Hwan Yoo ,  Jae-Hoon Joo

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C29/34

    摘要： A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

    摘要翻译： 本发明的半导体存储器件包括：主解码器，用于响应于第一解码信号，第一预充电信号和第二预充电信号产生字线使能信号; 响应于字线使能信号和第二解码信号的字线驱动信号的字线驱动器; 以及用于响应于命令信号产生第二预充电信号的电路。 响应于第一解码信号和第二预充电信号，字线驱动信号被顺序地去激活，以便减少地面噪声。

    Semiconductor memory devices including burn-in test circuits
    7.
    发明授权
    Semiconductor memory devices including burn-in test circuits 有权
    半导体存储器件包括老化测试电路

    公开(公告)号：US08441877B2

    公开(公告)日：2013-05-14

    申请号：US12731749

    申请日：2010-03-25

    申请人： Jong-Hyun Choi ,  Sang-Seok Kang

    发明人： Jong-Hyun Choi ,  Sang-Seok Kang

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

    摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

    摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。 控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。 第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。 还讨论了相关的操作方法。

    Fuse arrangement and integrated circuit device using the same
    9.
    发明授权
    Fuse arrangement and integrated circuit device using the same 失效
    保险丝布置和集成电路器件使用相同

    公开(公告)号：US07057217B2

    公开(公告)日：2006-06-06

    申请号：US10672035

    申请日：2003-09-26

    申请人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Sang-Ki Hwang

    发明人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Sang-Ki Hwang

    IPC分类号： H01L27/10

    CPC分类号： G11C17/143 ,  G11C29/785 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse circuit according to the present invention includes first and second fuses, each of which has a first end and a second end. The first and second ends of the first fuse are connected in a straight line. The first end of the second fuse is spaced by a first interval from the first end of the first fuse, and the second end thereof is spaced by a second interval from the second end of the first fuse. The first ends of the first and second fuses have the same widths as those of the second ends thereof. Alternatively, the first ends of the first and second fuses have narrower widths that those of the second ends thereof.

    摘要翻译： 根据本发明的熔丝电路包括第一和第二熔丝，每个熔丝具有第一端和第二端。 第一保险丝的第一端和第二端以直线连接。 第二保险丝的第一端与第一保险丝的第一端隔开第一间隔，并且第二保险丝的第二端与第一保险丝的第二端隔开第二间隔。 第一和第二熔断器的第一端具有与其第二端相同的宽度。 或者，第一和第二熔断器的第一端的宽度比第二端的宽度窄。