公开(公告)号：US06438042B1

公开(公告)日：2002-08-20

申请号：US09879076

申请日：2001-06-11

申请人： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

发明人： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

IPC分类号： G11C700

CPC分类号： G11C11/4094 ,  G11C7/12 ,  H01L27/10897

摘要： A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

摘要翻译： 半导体存储器件包括第一和第二隔离晶体管，用于将一对位线与读出放大器电路电连接/隔离;以及MOS晶体管，其具有与第一和第二隔离晶体管的源极之一共享的源极区域。 MOS晶体管可以用作位线升压电容器。

公开(公告)号：US06459636B2

公开(公告)日：2002-10-01

申请号：US09838358

申请日：2001-04-19

申请人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

发明人： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.

公开(公告)号：US06392938B1

公开(公告)日：2002-05-21

申请号：US09955635

申请日：2001-09-19

申请人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

发明人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

IPC分类号： G11C700

CPC分类号： G11C29/785

摘要： A semiconductor memory device comprises a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation. The mode control signal setting means sets a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.

摘要翻译： 半导体存储器件包括存储单元阵列，缺陷地址编程装置，冗余使能信号发生装置，输出装置和模式控制信号设置装置。 存储单元阵列包括多个存储单元。 缺陷地址编程装置响应于从外部施加的第一控制信号和地址信号，以封装级别编程多个存储器单元中的有缺陷的存储单元的冗余控制信号和缺陷地址。 当地址与缺陷地址一致时，冗余使能信号发生装置响应于冗余控制信号产生比较重合信号。 输出装置在测试操作期间响应于第二控制信号将比较重合信号输出到外部部分。 模式控制信号设置装置响应于从外部施加的命令信号和模式设置信号来设置第一和第二控制信号的状态。

公开(公告)号：US06345011B2

公开(公告)日：2002-02-05

申请号：US09758526

申请日：2001-01-10

申请人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

发明人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

IPC分类号： G11C800

CPC分类号： G11C7/10

摘要： A semiconductor memory device including a plurality of memory blocks having associated with one or more circuit blocks therearound, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between the adjacent memory blocks while first portions of the input/output lines of the second group are arranged within the circuit blocks around the adjacent memory blocks. Second portions of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks.

摘要翻译： 公开了一种包括与其周围的一个或多个电路块相关联的多个存储块的半导体存储器件，以及与存储器块相关联的多个输入/输出线。 输入/输出线分成至少第一组和第二组。 第一组的输入/输出线的第一部分被布置在相邻的存储块之间，而第二组的输入/输出线的第一部分被布置在邻近的存储块周围的电路块内。 第一组的输入/输出线的第二部分布置在存储块周围的电路块上，而第二组的输入/输出线的第二部分被布置在相邻的存储块之间。

公开(公告)号：US06438047B1

公开(公告)日：2002-08-20

申请号：US09908192

申请日：2001-07-18

申请人： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

发明人： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

IPC分类号： G11C700

CPC分类号： G11C29/846

摘要： A semiconductor memory device comprises a memory cell array, at least one redundant cell control, a sense amplifier, and at least one redundant cell. The memory cell array receives and outputs data through data I/O line groups. The redundant cell control stores a defective cell address, generates a redundant cell enable control signal when the defective cell address is equal to an input cell address, generates a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generates a redundant cell write control signal during a write operation in response to the redundant cell enable control signal. The sense amplifier is connected to an I/O line group commonly connected to the data I/O line groups, amplifies and outputs data outputted from the memory cell array during the read operation, and is disabled in response to the redundant cell read control signal. The redundant cell stores input data transferred to the I/O line group in response to the redundant cell write control signal and outputs stored data in response to the redundant cell read control signal.

摘要翻译： 半导体存储器件包括存储单元阵列，至少一个冗余单元控制，读出放大器和至少一个冗余单元。 存储单元阵列通过数据I / O线组接收和输出数据。 冗余单元控制存储故障单元地址，当缺陷单元地址等于输入单元地址时产生冗余单元使能控制信号，在读操作期间响应冗余单元使能控制信号产生冗余单元读控制信号 并且响应于冗余单元使能控制信号在写操作期间产生冗余单元写入控制信号。 感测放大器连接到通常连接到数据I / O线组的I / O线组，在读操作期间放大并输出从存储单元阵列输出的数据，并响应于冗余单元读取控制信号而被禁止 。 冗余单元响应于冗余单元写入控制信号存储传送到I / O线组的输入数据，并根据冗余单元读取控制信号输出存储的数据。

公开(公告)号：US09183910B2

公开(公告)日：2015-11-10

申请号：US13907223

申请日：2013-05-31

申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

IPC分类号： G11C11/16 ,  G11C7/12

CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。

公开(公告)号：US20080080285A1

公开(公告)日：2008-04-03

申请号：US11730275

申请日：2007-03-30

申请人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

发明人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40618

摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

摘要翻译： 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括：将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

公开(公告)号：US20060044912A1

公开(公告)日：2006-03-02

申请号：US11129073

申请日：2005-05-13

申请人： Byoung-Sul Kim ,  Yun-Sang Lee

发明人： Byoung-Sul Kim ,  Yun-Sang Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1042 ,  G11C11/406 ,  G11C11/40618

摘要： For refreshing a memory device, a refresh selection unit is enabled within a selected group of memory cells for refreshing at least one memory cell within the selected group in response to a refresh control signal and a refresh address signal from an external source. In addition, a normal operation circuit performs a normal operation on at least one memory cell of another group of memory cells while the at least one memory cell within the selected group is being refreshed to reduce refresh overhead.

摘要翻译： 为了刷新存储器件，刷新选择单元在所选择的存储器单元组内启用，用于响应于来自外部源的刷新控制信号和刷新地址信号刷新所选组中的至少一个存储器单元。 此外，正常操作电路对另一组存储器单元的至少一个存储单元执行正常操作，同时刷新所选组内的至少一个存储单元以减少刷新开销。

公开(公告)号：US06996754B1

公开(公告)日：2006-02-07

申请号：US09672223

申请日：2000-09-27

申请人： Yun-Sang Lee

发明人： Yun-Sang Lee

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing storage locations and for controlling internal operations, a first selection circuit for receiving the internal circuits in response to selection signals corresponding to test information signals, a second selection circuit for receiving output signals from the first selection circuit and output signals from a sense amplifier, and for opening an alternative one of transfer paths of the internal signals and the output signals in response to the selection signals, and a data output buffer for transferring output signals from the second selection signals to an outside of the device through data input/output pads.

摘要翻译： 公开了一种用于测试的集成电路装置。 该装置包括用于产生多个内部信号的多个内部电路，用于寻址存储位置和用于控制内部操作的内部信号，用于响应于与测试信息信号对应的选择信号接收内部电路的第一选择电路， 第二选择电路，用于接收来自第一选择电路的输出信号和来自读出放大器的输出信号，以及响应于选择信号打开内部信号和输出信号的传输路径中的另一个传输路径;以及数据输出缓冲器 用于通过数据输入/输出焊盘将输出信号从第二选择信号传送到设备的外部。

公开(公告)号：US20050243627A1

公开(公告)日：2005-11-03

申请号：US11105169

申请日：2005-04-12

申请人： Yun-Sang Lee ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40618

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。