公开(公告)号：US5484743A

公开(公告)日：1996-01-16

申请号：US394587

申请日：1995-02-27

申请人： Joe Ko ,  Chen-Chiu Hsue

发明人： Joe Ko ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66583 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.

摘要翻译： 本发明涉及形成用于超大规模集成器件的改进的MOSFET器件结构的方法。 使用离子注入直接在栅极下方形成局部自对准的穿透区域。 局部抗穿透区域减小了通道中的耗尽区域的膨胀，从而增加穿透电压。 局部抗穿透区域与栅极电极和源极/漏极区域自对准，使得即使对于亚微米器件也保持临界间隔。 沟道迁移率不降低，源极和漏极结电容减小。 本发明可用于N沟道或P沟道MOSFET器件，以及LDD（轻掺杂漏极）或非LDD器件中。

公开(公告)号：US5956590A

公开(公告)日：1999-09-21

申请号：US907242

申请日：1997-08-06

申请人： Yong-Fen Hsieh ,  Shu-Jen Chen ,  Joe Ko

发明人： Yong-Fen Hsieh ,  Shu-Jen Chen ,  Joe Ko

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/08

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/665

摘要： A field effect transistor which is not susceptible to mask edge detects at its gate spacer oxides. The transistor is formed upon a semiconductor substrate through successive layering of a gate oxide, a gate electrode and a gate cap oxide. A pair of curved gate spacer oxides are then formed covering opposite edges of the stack of the gate oxide, the gate electrode and the gate cap oxide. The semiconductor substrate is then etched to provide a smooth topographic transition from the gate spacer oxides to the etched semiconductor surface. Source/drain electrodes are then implanted into the etched semiconductor substrate and annealed to yield the finished transistor. A second embodiment of the field effect transistor possesses a polysilicon gate. Alter removal of the gate cap oxide, a metal layer may be deposited and sintered upon the polysilicon gate and the source/drain electrodes. The metal salicide layers formed upon the electrodes of the transistor have limited susceptibility to parasitic current leakage.

摘要翻译： 对栅极边缘不敏感的场效应晶体管在其栅极间隔氧化物处检测。 晶体管通过栅极氧化物，栅极电极和栅极氧化物的连续层叠形成在半导体衬底上。 然后形成一对弯曲的栅间隔氧化物，其覆盖栅极氧化物，栅极电极和栅极氧化物的堆叠的相对边缘。 然后蚀刻半导体衬底以提供从栅极间隔物氧化物到蚀刻的半导体表面的平滑的形貌转变。 然后将源极/漏极注入到蚀刻的半导体衬底中并退火以产生成品晶体管。 场效应晶体管的第二实施例具有多晶硅栅极。 改变栅极氧化物的去除，金属层可以沉积并烧结在多晶硅栅极和源极/漏极上。 形成在晶体管的电极上的金属硅化物层具有对寄生电流泄漏的敏感性的限制。

公开(公告)号：US5654569A

公开(公告)日：1997-08-05

申请号：US705649

申请日：1996-08-30

申请人： Joe Ko

发明人： Joe Ko

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836

摘要： A method of forming a retarded double diffused drain structure, and the resultant retarded double diffused drain structure, for a field effect transistor are described. A silicon substrate with field isolation regions and a gate structure is provided. A layer of photoresist is formed on the field isolation region, the silicon substrate, and the gate structure. The photoresist is patterned to expose the silicon substrate and the gate structure, but covers an area of the silicon substrate that is offset from the field isolation regions. A first ion implant is performed in a vertical direction in exposed regions of the silicon substrate, with suitable dopant having a high doping concentration. The photoresist is removed. A second ion implant is performed in a vertical direction in the silicon substrate, with suitable dopant with higher doping concentration than the first ion implant, in regions between the field isolation regions and the gate structure. The substrate is heated to drive in both the dopants.

摘要翻译： 描述形成延迟双扩散漏极结构的方法和所产生的延迟双扩散漏极结构用于场效应晶体管。 提供具有场隔离区域和栅极结构的硅衬底。 在场隔离区，硅衬底和栅极结构上形成一层光致抗蚀剂。 图案化光致抗蚀剂以暴露硅衬底和栅极结构，但是覆盖与衬底隔离区域偏移的硅衬底的区域。 在硅衬底的暴露区域中在垂直方向上执行第一离子注入，具有高掺杂浓度的合适的掺杂剂。 去除光致抗蚀剂。 在硅衬底中，在场隔离区域和栅极结构之间的区域中，在垂直方向上执行第二离子注入，具有比第一离子注入更高的掺杂浓度的合适掺杂剂。 衬底被加热以在两种掺杂剂中驱动。

公开(公告)号：US5646062A

公开(公告)日：1997-07-08

申请号：US374965

申请日：1995-01-19

申请人： Lee Chung Yuan ,  Joe Ko

发明人： Lee Chung Yuan ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0266

摘要： An improved semiconductor structure forms a series of FETs that are each connected between an input pad and ground for protecting the semiconductor device from an electrostatic discharge that may appear at the pad. Diffusions form alternate drain and source regions and are spaced apart at the surface of the device. Gate electrodes are located over the substrate between the diffusions so that the drain diffusion on one side of a gate also forms the drain for the FET on the one side and the source diffusion on the other side also forms the source diffusion for an FET on the other side. The electrical connection between the pad and the drain diffusions is formed by connections through the overlying insulation to a midpoint in the drain diffusion. Electrical connections between the gate and ground are formed by extending the conductive pattern that forms the gate. An electrical connection is made between the source diffusion and the gate electrode by a buried contact technique. A conductor is formed over the source diffusion as part of the process of forming the gate electrode, and the two electrodes are physically and conductively connected. The drain diffusions are made deeper than the source diffusions.

摘要翻译： 改进的半导体结构形成一系列FET，每个FET连接在输入焊盘和接地之间，用于保护半导体器件免受可能出现在焊盘处的静电放电。 扩散形成交替的漏极和源极区域并且在器件的表面处间隔开。 栅电极位于扩散之间的衬底之上，使得栅极一侧上的漏极扩散也在一侧形成FET的漏极，另一侧的源极扩散也形成FET上的源极扩散 另一边。 焊盘和漏极扩散之间的电连接通过穿过上覆绝缘体的连接到漏极扩散中的中点形成。 通过延伸形成栅极的导电图案来形成栅极和地之间的电连接。 通过掩埋接触技术在源极扩散和栅电极之间进行电连接。 在源极扩散上形成导体作为形成栅电极的过程的一部分，并且两个电极物理和导电连接。 漏极扩散比源扩散更深。

公开(公告)号：US5565369A

公开(公告)日：1996-10-15

申请号：US517723

申请日：1995-08-07

申请人： Joe Ko

发明人： Joe Ko

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836

摘要： A method of forming a retarded double diffused drain structure, and the resultant retarded double diffused drain structure, for a field effect transistor are described. A silicon substrate with field isolation regions and a gate structure is provided. A layer of photoresist is formed on the field isolation region, the silicon substrate, and the gate structure. The photoresist is patterned to expose the silicon substrate and the gate structure, but covers an area of the silicon substrate that is offset from the field isolation regions. A first ion implant is performed in a vertical direction in exposed regions of the silicon substrate, with suitable dopant having a high doping concentration. The photoresist is removed. A second ion implant is performed in a vertical direction in the silicon substrate, with suitable dopant with higher doping concentration than the first ion implant, in regions between the field isolation regions and the gate structure. The substrate is heated to drive in both the dopants.

摘要翻译： 描述形成延迟双扩散漏极结构的方法和所产生的延迟双扩散漏极结构用于场效应晶体管。 提供具有场隔离区域和栅极结构的硅衬底。 在场隔离区，硅衬底和栅极结构上形成一层光致抗蚀剂。 图案化光致抗蚀剂以暴露硅衬底和栅极结构，但是覆盖与衬底隔离区域偏移的硅衬底的区域。 在硅衬底的暴露区域中在垂直方向上执行第一离子注入，具有高掺杂浓度的合适的掺杂剂。 去除光致抗蚀剂。 在硅衬底中，在场隔离区域和栅极结构之间的区域中，在垂直方向上执行第二离子注入，具有比第一离子注入更高的掺杂浓度的合适掺杂剂。 衬底被加热以在两种掺杂剂中驱动。

公开(公告)号：US5514623A

公开(公告)日：1996-05-07

申请号：US387435

申请日：1995-02-13

申请人： Joe Ko ,  Bill Hsu

发明人： Joe Ko ,  Bill Hsu

IPC分类号： H01L23/485 ,  H01L21/283 ,  H01L21/3065

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05599 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S438/91

摘要： A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a polysilicon layer is formed on the substrate to act as a first contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forms large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, by direct contact to the first metal at the large contact pad area, and through the openings in the second insulator to the first metal interconnection. Finally, a passivation layer is formed over the second metal layer.

摘要翻译： 在硅衬底中形成用于集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 在衬底上形成多晶硅层的图案层，以作为集成电路的第一接触。 在多晶硅层上形成绝缘层，通过绝缘层形成到多晶硅层的开口。 在绝缘体上形成第一金属层，使得金属通过开口与多晶硅电连接，并且还形成大的接触焊盘区域。 第一金属被图案化以在大接触焊盘区域和集成电路之间形成电断路。 这种断开可防止在等离子体环境中的后续处理期间由于电荷积聚而对集成电路的电气损坏。 第二绝缘层被形成并图案化以提供到第一金属层的通孔的开口。 第二层金属形成在大的接触焊盘区域上并且在电断裂之上，使得第二金属通过在大的接触焊盘区域处直接接触第一金属并且通过在第二金属的开口处电连接到第一金属 第二绝缘体到第一金属互连。 最后，在第二金属层上形成钝化层。

公开(公告)号：US5473169A

公开(公告)日：1995-12-05

申请号：US406170

申请日：1995-03-17

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chung-Yuan Lee ,  Joe Ko

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chung-Yuan Lee ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L29/06

CPC分类号： H01L27/0259

摘要： A complementary-SCR electrostatic discharge protection circuit in a silicon substrate, coupling to I/O pads for bypassing electrostatic current of positive or negative polarity respect to power supply voltages V.sub.DD and V.sub.SS. The circuit comprises a first SCR and a second SCR each having an anode, a cathode, an anode gate and a cathode gate. The circuit of the present invention preferably includes a finger type layout structure for providing a larger capacity to bypass electrostatic current. It is also characterized by a base-emitter shorting design to avoid a V.sub.DD -to-V.sub.SS latch-up effect.

摘要翻译： 在硅衬底中的互补SCR静电放电保护电路，耦合到I / O焊盘，用于绕过电源电压VDD和VSS旁路正极或负极性的静电电流。 电路包括第一SCR和第二SCR，每个具有阳极，阴极，阳极栅极和阴极栅极。 本发明的电路优选地包括用于提供更大容量来绕过静电电流的手指型布局结构。 它还具有基极 - 发射极短路设计的特征，以避免VDD至VSS闭锁效应。

公开(公告)号：US5460987A

公开(公告)日：1995-10-24

申请号：US365044

申请日：1994-12-27

申请人： Jemmy Wen ,  Water Lur ,  Joe Ko

发明人： Jemmy Wen ,  Water Lur ,  Joe Ko

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/112 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/41766 ,  H01L21/823418 ,  H01L27/112 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66787 ,  H01L29/78

摘要： This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.

摘要翻译： 本发明描述了一种潜水通道装置结构，以及使用形成在与在同一硅衬底中形成的浅垂直沟槽的硅衬底中形成的深垂直沟槽形成潜水通道器件结构的方法。 深垂直沟槽填充有第一重掺杂多晶硅以形成场效应晶体管的源极和漏极。 浅的垂直沟槽用第二高掺杂多晶硅填充以形成晶体管的栅极。 器件结构提供了降低的漏极和源极电阻，当器件被缩放到更小的尺寸时，其保持几乎恒定。 器件结构还提供减少的漏电流和平面形貌。 当设备缩放到更小的尺寸时，器件结构形成大的有效通道宽度。

公开(公告)号：US5393701A

公开(公告)日：1995-02-28

申请号：US44931

申请日：1993-04-08

申请人： Joe Ko ,  Bill Hsu

发明人： Joe Ko ,  Bill Hsu

IPC分类号： H01L23/485 ,  H01L21/443

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05599 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S438/91

摘要： A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a conductive polysilicon is formed on the substrate to act as a first conductive contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forming large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, via direct contact to the first metal at the large contact pad area, and through the openings in the second insulator to the first metal interconnection. Finally, a passivation layer is formed over the second metal layer.

摘要翻译： 在硅衬底中形成用于集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 导电多晶硅的图案层形成在衬底上以用作集成电路的第一导电接触。 在多晶硅层上形成绝缘层，通过绝缘层形成到多晶硅层的开口。 在绝缘体上形成第一金属层，使得金属通过开口电连接到多晶硅，并且还形成大的接触焊盘区域。 第一金属被图案化以在大接触焊盘区域和集成电路之间形成电断路。 这种断开可防止在等离子体环境中的后续处理期间由于电荷积聚而对集成电路的电气损坏。 第二绝缘层被形成并图案化以提供到第一金属层的通孔的开口。 第二层金属形成在大的接触焊盘区域上并且在电断裂之上，使得第二金属通过与大接触焊盘区域处的第一金属直接接触而电连接到第一金属，并通过 第二绝缘体到第一金属互连。 最后，在第二金属层上形成钝化层。

公开(公告)号：US5308780A

公开(公告)日：1994-05-03

申请号：US94990

申请日：1993-07-22

申请人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

发明人： Jih W. Chou ,  Joe Ko ,  Chun Y. Chang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of forming an integrated circuit field effect transistor with surface counter-doped lightly doped drain regions is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions. A thin layer of silicon oxide is deposited over the surface of the polysilicon gate electrode structure and is anisotropically etched to form ultra thin spacers on the sidewalls of the polysilicon gate electrode structure. A third ion implantation is performed with no tilt angle to complete formation of the lightly doped drain regions. A glasseous layer is deposited over all surfaces of the substrate and flowed followed by metallization and passivation to complete manufacture of the integrated circuit.

摘要翻译： 描述了一种形成具有表面反掺杂轻掺杂漏极区域的集成电路场效应晶体管的方法。 在硅衬底上形成栅氧化硅层。 一层多晶硅沉积在栅极氧化硅层上并被蚀刻以形成栅电极结构。 以倾斜角度执行第一离子注入，以在半导体衬底中形成轻掺杂漏极区域，其中轻掺杂漏极区域被栅电极结构部分地重叠。 以比第一离子注入更大的倾斜角度和更低的能量执行第二离子注入，其中第二离子注入反掺杂轻掺杂的漏极区的表面以形成非常轻掺杂的漏极层，从而使轻掺杂漏极区 埋葬地区。 氧化硅薄层沉积在多晶硅栅电极结构的表面上，并被各向异性蚀刻以在多晶硅栅电极结构的侧壁上形成超薄间隔物。 执行没有倾斜角的第三离子注入以完成轻掺杂漏极区的形成。 在基板的所有表面上沉积一层胶层，然后流动，随后进行金属化和钝化以完成集成电路的制造。