公开(公告)号：US5594704A

公开(公告)日：1997-01-14

申请号：US419566

申请日：1995-04-10

申请人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1072

摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止写入期望的位，如果数据写入应该是数据写入时，可以将数据集中写入所选择的存储器单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。

公开(公告)号：US5731727A

公开(公告)日：1998-03-24

申请号：US527968

申请日：1995-09-14

申请人： Hisashi Iwamoto ,  Yasuhiro Konishi

发明人： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC分类号： G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K19/096 ,  H03L7/081 ,  H03K5/14 ,  H03L1/00

CPC分类号： H03L7/081 ,  H03K5/133

摘要： A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.

摘要翻译： 控制晶体管与电压控制延迟电路中的偏置产生电路的输入晶体管并联连接。 电源电位Vcc由施加到控制晶体管的栅极的分压电阻器分压。 电源电位Vcc的降低导致流向控制晶体管的电流Ib的减少，流入延迟时间可变元件的电流Ic = Ia + Ib。 当电源电位Vcc减小时，延迟时间可变元件由于时钟信号的较小振幅而变短的延迟时间的因子被延迟时间可变元件的延迟时间的因数变得更长 由于流过其的较小的电流Ic。 因此，可以将延迟时间段的变化抑制到低水平。

公开(公告)号：US6151273A

公开(公告)日：2000-11-21

申请号：US362667

申请日：1999-07-29

申请人： Hisashi Iwamoto ,  Takeshi Kajimoto

发明人： Hisashi Iwamoto ,  Takeshi Kajimoto

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/18 ,  G11C2207/229

摘要： A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

摘要翻译： 提供了能够提高实质的传输速率的同步半导体存储器件。 响应于紧跟在动作命令之后的写入命令，控制信号产生电路将无效使能信号应用于读取的前置放大器和写入缓冲器。 响应于写入命令和预充电命令，控制信号产生电路产生有效使能信号，读取的前置放大器和写入缓冲器将存储在FIFO中的数据写入存储单元。 由于在接收到动作命令之后的写入命令时不执行后期写入，因此可以防止数据向不想要的地址的错误写入。

公开(公告)号：US6118730A

公开(公告)日：2000-09-12

申请号：US295361

申请日：1999-04-21

申请人： Takashi Kubo ,  Yasumitsu Murai ,  Hisashi Iwamoto

发明人： Takashi Kubo ,  Yasumitsu Murai ,  Hisashi Iwamoto

IPC分类号： G11C11/407 ,  G11C7/22 ,  H03D13/00 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  G11C8/00

CPC分类号： H03L7/089 ,  G11C7/22 ,  H03D13/004 ,  H03K5/26 ,  H03L7/0814

摘要： The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.

摘要翻译： 相位比较器接收接收第一输入信号的缓冲器的输出和接收第二输入信号的缓冲器的输出，并且作为相位比较的结果输出信号SLOW，FAST。 相位比较器包括用于放大两个输入信号之间的相位差的波形处理电路和用于通过波形处理电路放大的相位差进行相位比较的比较电路，并输出信号SLOW，FAST。 由于波形处理电路的功能，可以显着提高相位比较器的性能，而不必大幅提高比较电路的性能。

公开(公告)号：US5940344A

公开(公告)日：1999-08-17

申请号：US53058

申请日：1998-04-01

申请人： Yasumitsu Murai ,  Wataru Sakamoto ,  Hisashi Iwamoto

发明人： Yasumitsu Murai ,  Wataru Sakamoto ,  Hisashi Iwamoto

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/00

CPC分类号： G11C7/22

摘要： In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.

摘要翻译： 在内部时钟信号发生电路中，用于检测外部时钟信号和内部时钟信号之间的相位差的相位比较器包括相对于信号线的晶体管和电容器，通过该信号线发送对应于外部时钟信号的时钟信号 以及相对于信号线的晶体管和电容器，通过该晶体管和电容器发送与内部时钟信号对应的时钟信号。 具有两个信号线的信号的滞后相位的信号的上升定时变得更加平缓。 结果，相位差增大，相位比较器可以高精度地比较相位。

公开(公告)号：US20130039134A1

公开(公告)日：2013-02-14

申请号：US13566779

申请日：2012-08-03

申请人： Hisashi Iwamoto ,  Yuji Yano ,  Kazunari Inoue

发明人： Hisashi Iwamoto ,  Yuji Yano ,  Kazunari Inoue

IPC分类号： G11C7/22

CPC分类号： G11C7/1069 ,  G11C7/1006 ,  G11C7/1096 ,  G11C7/222

摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

摘要翻译： 半导体器件包括多个存储器阵列和多个存储器阵列控制电路。 多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路 读/写控制电路。

公开(公告)号：US06763079B1

公开(公告)日：2004-07-13

申请号：US09252910

申请日：1999-02-19

申请人： Hisashi Iwamoto

发明人： Hisashi Iwamoto

IPC分类号： H04L708

CPC分类号： G11C29/12015 ,  G01R31/31725 ,  G01R31/31727 ,  G11C29/02 ,  G11C29/50012 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00241 ,  H03L7/0814 ,  H03L7/089

摘要： A shift register which outputs a delay control signal for a delay line is made controllable at a test mode by a TEST MODE address buffer receiving an external address as a control signal and a phase comparator. Thus whether the delay of the delay line is correctly controlled or not can be confirmed through observation of an internal clock signal int. CLK output from an output buffer at the test and an external clock signal ext. CLK.

摘要翻译： 输出用于延迟线的延迟控制信号的移位寄存器通过接收作为控制信号的外部地址的TEST MODE地址缓冲器和相位比较器在测试模式下被控制。 因此，可以通过观察内部时钟信号int来确认延迟线的延迟是否被正确控制。 来自测试时的输出缓冲器的CLK输出和外部时钟信号分频。 CLK。

公开(公告)号：US06741507B2

公开(公告)日：2004-05-25

申请号：US10224343

申请日：2002-08-21

申请人： Hisashi Iwamoto

发明人： Hisashi Iwamoto

IPC分类号： G11C700

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/222

摘要： In a DLL circuit between a phase comparator and a digital filter there is provided a signal switching portion preventing control signals UP and DOWN from being transmitted after a clock enable signal extCKE is activated and before a predetermined period of time elapses. Thus after a semiconductor device returns from a power down mode and before a predetermined period of time elapses it continues to stop updating an amount of delay of a delay line. Thus before an internal power supply potential stabilizes the delay line does not have a varying amount of delay and as a result the semiconductor device can output data at a timing free of significant fluctuation.

摘要翻译： 在相位比较器和数字滤波器之间的DLL电路中，提供了一个信号切换部分，该信号切换部分防止在时钟使能信号extCKE被激活之后并在经过预定时间段之前传输控制信号UP和DOWN。 因此，在半导体器件从断电模式返回并且在经过预定时间段之前，它继续停止更新延迟线的延迟量。 因此，在内部电源电位稳定之前，延迟线不具有变化的延迟量，因此半导体器件可以在没有显着波动的时刻输出数据。

公开(公告)号：US06720807B1

公开(公告)日：2004-04-13

申请号：US10377738

申请日：2003-03-04

申请人： Takashi Kubo ,  Hisashi Iwamoto

发明人： Takashi Kubo ,  Hisashi Iwamoto

IPC分类号： H03L700

CPC分类号： H03K19/0005 ,  G06F1/10 ,  H03L7/0812

摘要： An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.

摘要翻译： 阻抗调整电路根据外部施加的阻抗控制信号产生内部阻抗调整信号和阻抗调整输入信号。 数据处理电路与内部时钟信号同步地解码内部阻抗调整信号，以产生5位的输出缓冲器驱动信号。 当输出缓冲器驱动信号被施加到后级的输出电路以及DLL电路中的输出复制电路时，在调节输出阻抗之后调整输出复制电路的阻抗。

公开(公告)号：US06184738B2

公开(公告)日：2001-02-06

申请号：US09019199

申请日：1998-02-05

申请人： Hisashi Iwamoto ,  Aiko Nishino ,  Wataru Sakamoto

发明人： Hisashi Iwamoto ,  Aiko Nishino ,  Wataru Sakamoto

IPC分类号： H03L500

CPC分类号： H03K19/018528

摘要： An input buffer of a semiconductor device is provided. A first voltage shift circuit converts an input signal formed of a low amplitude logic signal overlapping 1.65V or 2.9V to a first signal formed of a complimentary signal formed of the low amplitude logic signal overlapping 2.9V or 1.65V. A second voltage shift circuit converts a reference potential of 1.65V or 2.9V to a second signal of 2.9V or 1.65V. A differential amplifier compares the reference potential with the input signal when the reference potential is 1.65V, and compares the first signal and the second signal when the reference potential is 2.9V. The input buffer thus operates normally whichever of 1.65V and 2.9V is the reference potential.

摘要翻译： 提供半导体器件的输入缓冲器。第一电压移位电路将由1.65V或2.9V重叠的低幅度逻辑信号形成的输入信号转换成由与低幅度逻辑信号形成的互补信号形成的第一信号重叠2.9 V或1.65V。 第二电压移位电路将1.65V或2.9V的参考电位转换为2.9V或1.65V的第二信号。 当参考电位为1.65V时，差分放大器将参考电位与输入信号进行比较，当参考电位为2.9V时，比较第一信号和第二信号。 因此，输入缓冲器通常正常为1.65V和2.9V为参考电位。