-
公开(公告)号：US5867446A
公开(公告)日：1999-02-02
申请号：US332626
申请日：1994-10-31
CPC分类号： G11C7/1072 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
-
公开(公告)号：US5594704A
公开(公告)日：1997-01-14
申请号：US419566
申请日：1995-04-10
CPC分类号： G11C8/12 , G11C7/10 , G11C7/1006 , G11C7/1072
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止写入期望的位，如果数据写入应该是数据写入时，可以将数据集中写入所选择的存储器单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。
-
公开(公告)号：US5384745A
公开(公告)日：1995-01-24
申请号：US46333
申请日：1993-04-14
CPC分类号： G11C7/1072 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止对所需位的写入，如果数据写入应当是数据写入时，可以将数据集中写入所选存储单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。
-
公开(公告)号：US6151273A
公开(公告)日：2000-11-21
申请号：US362667
申请日：1999-07-29
申请人： Hisashi Iwamoto , Takeshi Kajimoto
发明人： Hisashi Iwamoto , Takeshi Kajimoto
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1072 , G11C8/18 , G11C2207/229
摘要： A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.
摘要翻译： 提供了能够提高实质的传输速率的同步半导体存储器件。 响应于紧跟在动作命令之后的写入命令，控制信号产生电路将无效使能信号应用于读取的前置放大器和写入缓冲器。 响应于写入命令和预充电命令，控制信号产生电路产生有效使能信号，读取的前置放大器和写入缓冲器将存储在FIFO中的数据写入存储单元。 由于在接收到动作命令之后的写入命令时不执行后期写入，因此可以防止数据向不想要的地址的错误写入。
-
公开(公告)号：US5391979A
公开(公告)日：1995-02-21
申请号：US135512
申请日：1993-10-13
CPC分类号： G05F3/30
摘要： The constant current generating circuit includes a high resistance element for generating a very small current. This very small current is supplied to a first MOS transistor having a sufficiently large gate width to gate length ratio. The gate-source voltage of the first MOS transistor becomes its threshold voltage VTH, and the voltage applied across a resistance connected between the gate of the first MOS transistor and the ground line is set to a constant value VTH. Thus, a constant current is normally passed through the resistance. Since the very small current is supplied from the high resistance element which is normally turned on, regardless of the change of the power supply voltage, a constant current can be generated stably.
摘要翻译： 恒定电流产生电路包括用于产生非常小的电流的高电阻元件。 这种非常小的电流被提供给具有足够大的栅极宽度与栅极长度比的第一MOS晶体管。 第一MOS晶体管的栅极 - 源极电压变为其阈值电压VTH，并且连接在第一MOS晶体管的栅极与地线之间的电阻上施加的电压被设定为恒定值VTH。 因此，恒定电流通常通过电阻。 由于从通常导通的高电阻元件提供非常小的电流，与电源电压的变化无关，所以能够稳定地产生恒定的电流。
-
公开(公告)号：US07903460B2
公开(公告)日：2011-03-08
申请号：US12398794
申请日：2009-03-05
申请人： Takeshi Kajimoto
发明人： Takeshi Kajimoto
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C2211/5641
摘要： The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.
摘要翻译： 本发明提供一种能够以足够小的分割单位实现擦除/写入操作，同时将芯片面积的增加抑制到最小并且缩短擦除时间的非易失性存储器。 提供两个物理擦除状态和逻辑擦除状态作为每个存储单元的阈值电压分布状态。 在逻辑擦除状态下，存储单元的阈值电压准则被转移到高于物理擦除状态的状态。 当执行放置在物理擦除状态的存储单元的数据重写时，执行逻辑擦除并将阈值电压标准转移到高电压电平。 逻辑擦除简单地移动阈值电压准则的电压电平。 由于积存在存储单元中的电荷不移动，所以可以在高速和短时间内进行擦除。
-
7.发明授权Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage 有权写入根据阈值电压电平变化存储信息的非易失性半导体存储器件的方法公开(公告)号：US07376016B2
公开(公告)日：2008-05-20
申请号：US11488621
申请日：2006-07-19
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3459
摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.
摘要翻译： 在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器 小区阈值电压和这样检测的存储单元经受附加写入。 可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。 所有存储单元可以准确地设置其各自的阈值电压。
-
公开(公告)号：US06998879B2
公开(公告)日：2006-02-14
申请号：US10394276
申请日：2003-03-24
申请人： Takeshi Kajimoto
发明人： Takeshi Kajimoto
IPC分类号： H03K5/22
CPC分类号： H04L25/061 , H03K5/086
摘要： An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.
摘要翻译： DRAM中的输入电路包括放大输入信号的电位和参考电位之间的电位差的差分放大电路，输出差分放大电路的输出信号的反相信号的反相器，保持输出信号的锁存电路 在前一周期中，以及两个电阻元件，用于根据锁存电路的输出信号切换参考电位。 因此，根据前一周期中的输入信号的逻辑电平来切换参考电位，从而允许准确地确定输入信号的逻辑电平。
-
公开(公告)号：US5446418A
公开(公告)日：1995-08-29
申请号：US147268
申请日：1993-11-05
申请人： Motoko Hara , Takeshi Kajimoto
发明人： Motoko Hara , Takeshi Kajimoto
IPC分类号： H03K3/354 , G11C11/407 , G11C11/408 , H03K3/03 , H03K3/353
CPC分类号： H03K3/0315
摘要： A ring oscillator according to the invention includes a plurality of inverters cascade-connected between an input node and an output node. Each inverter includes four transistors connected in series between a power supply node and a ground node. A first pair of transistors each have a channel sized to have an input capacitance for delaying the signal of a preceding stage inverter for a prescribed time period. A second pair of transistors are coupled to a current mirror circuit and limits current flowing through the first pair of transistors. Thus, power consumption for obtaining a signal in a prescribed cycle is reduced.
摘要翻译： 根据本发明的环形振荡器包括级联连接在输入节点和输出节点之间的多个反相器。 每个逆变器包括串联在电源节点和接地节点之间的四个晶体管。 第一对晶体管每个具有通道，其尺寸设置成具有用于将前级反相器的信号延迟规定时间段的输入电容。 第二对晶体管耦合到电流镜电路并限制流过第一对晶体管的电流。 因此，减少了在规定的周期内获得信号的功耗。
-
10.发明授权Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection 失效大规模集成电路器件，例如具有改进的旁路，冗余和单元集成电路互连布置的晶片刻度存储器
公开(公告)号：US5084838A
公开(公告)日：1992-01-28
申请号：US391783
申请日：1989-08-09
CPC分类号： G11C29/006 , G11C8/12
摘要： A plurality of unit integrated circuits mounted on a large-scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, it is possible to effectively couple together all unit integrated circuits which are judged to be normal among a plurality of unit integrated circuits disposed along one row, for example. Improved redundancy arrangements are also provided, including first and second redundant elements for the unit integrated circuits, to effectively utilize the normal elements in the unit integrated circuits. Further, an improved arrangement for hierarchically connecting together the outputs of all the unit circuit blocks is provided which reduces the signal line load for the memory device.
摘要翻译： 安装在大规模集成电路装置（例如，晶片刻度存储器）上的多个单元集成电路各自设置有旁路电路，其选择性地缩短相应的单元集成电路中的输入和输出节点。 通过选择性地使旁路电路进入传送状态，例如可以将沿着一行布置的多个单元集成电路中被判断为正常的所有单元集成电路有效地耦合在一起。 还提供了改进的冗余布置，包括用于单元集成电路的第一和第二冗余元件，以有效地利用单元集成电路中的正常元件。 此外，提供了用于将所有单元电路块的输出分层连接在一起的改进布置，其减少了存储器件的信号线负载。
-
-
-
-
-
-
-
-
-
搜索结果
38 条记录 (耗时 0.034 秒)
