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    POWER SEMICONDUCTOR DEVICE
    31.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权
    功率半导体器件

    公开(公告)号：US20140225114A1

    公开(公告)日：2014-08-14

    申请号：US14346466

    申请日：2012-06-07

    申请人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Kazuyasu Nishikawa

    发明人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Kazuyasu Nishikawa

    IPC分类号： H01L23/60 ,  H01L27/02

    CPC分类号： H01L23/60 ,  H01L27/0296 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.

    摘要翻译： 功率半导体器件包括形成为围绕漂移层表面上的多个感测阱的第二导电型感测外周阱，选择性地形成在主电池阱的表面上的第一导电型主电池源区， 选择性地形成在感测阱的表面上的第一导电型感测源极区，选择性地形成在感测外周阱的表面上的第一导电型电容器下电极区域，形成在沟道区域上的栅极绝缘膜 形成在栅极绝缘膜上的栅电极，以及与感测阱和感测源区以及感应外周阱和电容器下电极区电连接的检测焊盘。

    Semiconductor device formed on insulating layer and method of manufacturing the same
    36.
    发明授权
    Semiconductor device formed on insulating layer and method of manufacturing the same 失效
    绝缘层上形成的半导体器件及其制造方法

    公开(公告)号：US06653656B2

    公开(公告)日：2003-11-25

    申请号：US10336758

    申请日：2003-01-06

    申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

    发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

    IPC分类号： H01L2904

    CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

    摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

    摘要翻译： 在具有SOI结构的半导体器件及其制造方法中，可以防止寄生晶体管的影响，并且与制造过程相关的缺点不会产生。 在该半导体器件中，半导体层的上侧部分是圆形的。 由此，可以防止半导体层的上侧部分的电场集中。 结果，可以防止寄生晶体管的阈值电压的降低，使得寄生晶体管不会对正常晶体管的亚阈值特性产生不利影响。 通过设置U形截面的凹部，当蚀刻用于图案化的栅电极时，可以防止产生蚀刻残留。 因此，不会在制造过程中引起缺点。

    Semiconductor device
    38.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09202940B2

    公开(公告)日：2015-12-01

    申请号：US14239375

    申请日：2012-07-31

    申请人： Tsuyoshi Kawakami ,  Yoshiyuki Nakaki ,  Yoshio Fujii ,  Hiroshi Watanabe ,  Shuhei Nakata ,  Kohei Ebihara ,  Akihiko Furukawa

    发明人： Tsuyoshi Kawakami ,  Yoshiyuki Nakaki ,  Yoshio Fujii ,  Hiroshi Watanabe ,  Shuhei Nakata ,  Kohei Ebihara ,  Akihiko Furukawa

    IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L29/861 ,  H01L29/16

    CPC分类号： H01L29/8725 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/8611 ,  H01L29/872

    摘要： A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.

    摘要翻译： 具有高击穿电压和高可靠性的半导体器件，而不形成具有高定位精度的嵌入式注入层。 半导体器件包括形成在第一导电类型的半导体层的表面层上的第二导电类型的有源区的基底，以构成半导体元件; 保护环作为多个第一导电类型的第一杂质区域，形成在半导体层的表面层上彼此间隔开以在平面图中分别包围基底; 以及作为第二导电类型的第二杂质区域的嵌入式注入层，其嵌入在半导体层的表面层中，以连接多个保护环的至少两个底部。

    SEMICONDUCTOR DEVICE
    40.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150048384A1

    公开(公告)日：2015-02-19

    申请号：US14387727

    申请日：2013-02-26

    申请人： Rina Tanaka ,  Akihiko Furukawa ,  Masayuki Imaizumi ,  Yuji Abe

    发明人： Rina Tanaka ,  Akihiko Furukawa ,  Masayuki Imaizumi ,  Yuji Abe

    IPC分类号： H01L29/16 ,  H01L29/47 ,  H01L29/872

    CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/36 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/872

    摘要： In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn diode portion to turn on, resulting in a problem that resistance to surge currents is not sufficiently ensured. In order to solve this problem, in the wide-band-gap JBS diode, a pn junction of the pn diode is formed away from the Schottky electrode, and well regions are formed so as to have a width narrowed at a portion away from the Schottky electrode.

    摘要翻译： 在使用宽带隙半导体的JBS二极管中，宽带隙半导体具有大的内置电压，这有时使pn二极管部分导通困难，导致不能充分确保对浪涌电流的抵抗力的问题 。 为了解决这个问题，在宽带隙JBS二极管中，pn二极管的pn结远离肖特基电极形成，阱区形成为在远离 肖特基电极。