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公开(公告)号:US08969960B2
公开(公告)日:2015-03-03
申请号:US14346466
申请日:2012-06-07
IPC分类号: H01L29/76 , H01L29/94 , H01L23/60 , H01L29/66 , H01L29/78 , H01L27/02 , H01L29/06 , H01L29/16
CPC分类号: H01L23/60 , H01L27/0296 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7803 , H01L29/7804 , H01L29/7811 , H01L29/7815 , H01L2924/0002 , H01L2924/00
摘要: A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.
摘要翻译: 功率半导体器件包括形成为围绕漂移层表面上的多个感测阱的第二导电型感测外周阱,选择性地形成在主电池阱的表面上的第一导电型主电池源区, 选择性地形成在感测阱的表面上的第一导电型感测源极区,选择性地形成在感测外周阱的表面上的第一导电型电容器下电极区域,形成在沟道区域上的栅极绝缘膜 形成在栅极绝缘膜上的栅电极,以及与感测阱和感测源区以及感应外周阱和电容器下电极区电连接的检测焊盘。
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公开(公告)号:US20140225114A1
公开(公告)日:2014-08-14
申请号:US14346466
申请日:2012-06-07
CPC分类号: H01L23/60 , H01L27/0296 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7803 , H01L29/7804 , H01L29/7811 , H01L29/7815 , H01L2924/0002 , H01L2924/00
摘要: A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.
摘要翻译: 功率半导体器件包括形成为围绕漂移层表面上的多个感测阱的第二导电型感测外周阱,选择性地形成在主电池阱的表面上的第一导电型主电池源区, 选择性地形成在感测阱的表面上的第一导电型感测源极区,选择性地形成在感测外周阱的表面上的第一导电型电容器下电极区域,形成在沟道区域上的栅极绝缘膜 形成在栅极绝缘膜上的栅电极,以及与感测阱和感测源区以及感应外周阱和电容器下电极区电连接的检测焊盘。
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3.
公开(公告)号:US20140001472A1
公开(公告)日:2014-01-02
申请号:US13995993
申请日:2011-05-18
CPC分类号: H01L21/02529 , H01L21/8213 , H01L27/0629 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/872
摘要: A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.
摘要翻译: 一种碳化硅半导体器件,包括测量碳化硅半导体元件的温度的SBD。 碳化硅半导体器件包括形成在碳化硅外延衬底上的MOSFET和测量MOSFET的温度的SBD部分。 SBD部分包括在碳化硅漂移层的表面部分中的n型阴极区域; 在阴极区域形成的阳极钛电极,用作肖特基电极的电极; 形成在碳化硅漂移层的表面部分中以与阴极区接触的n型阴极接触区域,其浓度高于阴极区域; 形成在阴极接触区域上的阴极欧姆电极; 以及形成在碳化硅漂移层内以围绕阴极区域和阴极接触区域的周边的第一p型阱区域。
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公开(公告)号:US20150108564A1
公开(公告)日:2015-04-23
申请号:US14400025
申请日:2013-03-12
申请人: Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
发明人: Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
IPC分类号: H01L29/78 , H01L29/16 , H01L29/423 , H01L29/10 , H01L29/08
CPC分类号: H01L29/7802 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/66068 , H01L29/66893 , H01L29/7813 , H01L29/7827 , H01L29/7836 , H01L29/8083
摘要: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
摘要翻译: MOSFET的源极区域包括:源极接触区域,连接到源极焊盘; 源极延伸区域,其邻近阱区域中的沟道区域; 以及源极电阻控制区域,其布置在源极延伸区域和源极接触区域之间。 源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。 这三个区域串联连接在源极区和阱区中的沟道区之间。
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公开(公告)号:US09525057B2
公开(公告)日:2016-12-20
申请号:US14400025
申请日:2013-03-12
申请人: Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
发明人: Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
IPC分类号: H01L29/08 , H01L29/78 , H01L21/04 , H01L29/10 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/808 , H01L29/16
CPC分类号: H01L29/7802 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/66068 , H01L29/66893 , H01L29/7813 , H01L29/7827 , H01L29/7836 , H01L29/8083
摘要: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
摘要翻译: MOSFET的源极区域包括:源极接触区域,连接到源极焊盘; 源极延伸区域,其邻近阱区域中的沟道区域; 以及源极电阻控制区域,其布置在源极延伸区域和源极接触区域之间。 源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。 这三个区域串联连接在源极区和阱区中的沟道区之间。
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公开(公告)号:US09293572B2
公开(公告)日:2016-03-22
申请号:US13806534
申请日:2010-06-24
申请人: Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
发明人: Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
CPC分类号: H01L29/78 , H01L21/0485 , H01L27/088 , H01L29/0696 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7805 , H01L29/7815
摘要: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.
摘要翻译: 在具有感测焊盘的高速开关电力半导体器件中,由于位移电流通过其流动路径而具有电阻,在感测焊盘下的阱区域的开关操作期间产生高电压,由此功率半导体器件有时会分解 通过诸如栅极绝缘膜的薄绝缘膜的电介质击穿。 在根据本发明的功率半导体器件中,感测焊盘井接触孔设置在位于感测焊盘下方的阱区上,并穿透比栅极绝缘膜更厚的场绝缘膜以连接到源极焊盘,从而提高可靠性。
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公开(公告)号:US09111751B2
公开(公告)日:2015-08-18
申请号:US13995993
申请日:2011-05-18
IPC分类号: H01L23/58 , H01L21/02 , H01L21/82 , H01L27/06 , H01L29/66 , H01L29/78 , H01L29/872 , H01L29/47 , H01L29/16 , H01L29/45 , H01L29/06
CPC分类号: H01L21/02529 , H01L21/8213 , H01L27/0629 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/872
摘要: A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.
摘要翻译: 一种碳化硅半导体器件,包括测量碳化硅半导体元件的温度的SBD。 碳化硅半导体器件包括形成在碳化硅外延衬底上的MOSFET和测量MOSFET的温度的SBD部分。 SBD部分包括在碳化硅漂移层的表面部分中的n型阴极区域; 在阴极区域形成的阳极钛电极,用作肖特基电极的电极; 形成在碳化硅漂移层的表面部分中以与阴极区接触的n型阴极接触区域,其浓度高于阴极区域; 形成在阴极接触区域上的阴极欧姆电极; 以及形成在碳化硅漂移层内以围绕阴极区域和阴极接触区域的周边的第一p型阱区域。
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公开(公告)号:US20130168700A1
公开(公告)日:2013-07-04
申请号:US13806534
申请日:2010-06-24
申请人: Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
发明人: Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
IPC分类号: H01L29/78
CPC分类号: H01L29/78 , H01L21/0485 , H01L27/088 , H01L29/0696 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7805 , H01L29/7815
摘要: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.
摘要翻译: 在具有感测焊盘的高速开关电力半导体器件中,由于位移电流通过其流动路径而具有电阻,在感测焊盘下的阱区域的开关操作期间产生高电压,由此功率半导体器件有时会分解 通过诸如栅极绝缘膜的薄绝缘膜的电介质击穿。 在根据本发明的功率半导体器件中,感测焊盘井接触孔设置在位于感测焊盘下方的阱区上,并穿透比栅极绝缘膜更厚的场绝缘膜以连接到源极焊盘,从而提高可靠性。
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公开(公告)号:US08716717B2
公开(公告)日:2014-05-06
申请号:US13816511
申请日:2011-04-15
申请人: Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人: Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号: H01L29/12
CPC分类号: H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要: A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
摘要翻译: 在活性区域附近形成包括具有低浓度P型杂质的多个P型注入层的RESURF层。 RESURF层包括从P型基底侧依次布置以围绕P型基底的第一RESURF层,第二RESURF层,第三RESURF层,第四RESURF层和第五RESURF层。 第二RESURF层配置有具有等于第一RESURF层的注入量的小区域,并且具有与第三RESURF层的注入量相等的注入量的小区域被交替排列成多个。 第四RESURF层配置有具有等于第三RESURF层的注入量的小区域,并且具有与第五RESURF层的注入量相等的注入量的小区域被交替排列成多个。
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公开(公告)号:US09006819B2
公开(公告)日:2015-04-14
申请号:US13639738
申请日:2011-02-08
申请人: Shiro Hino , Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Akihiko Furukawa , Yukiyasu Nakao , Masayuki Imaizumi
发明人: Shiro Hino , Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Akihiko Furukawa , Yukiyasu Nakao , Masayuki Imaizumi
IPC分类号: H01L29/66 , H01L29/10 , H01L29/78 , H01L29/861 , H01L29/06 , H01L29/16 , H01L29/40 , H01L29/423 , H01L29/739
CPC分类号: H01L29/1095 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1608 , H01L29/402 , H01L29/42372 , H01L29/66068 , H01L29/7395 , H01L29/7805 , H01L29/7811 , H01L29/8611
摘要: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.
摘要翻译: 半导体器件包括第一导电类型的半导体衬底,形成在半导体衬底的第一主表面上的第一导电类型的漂移层,形成为围绕电池的第二导电类型的第二阱区域 漂移层的区域和用于通过设置成穿过第二阱区域上的栅极绝缘膜设置的第一阱接触孔电连接第二阱区域和电池区域的源极区域的源极焊盘,提供第二阱接触孔 以穿透第二阱区域上的场绝缘膜和源极接触孔。
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