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    SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
    4.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME 有权
    硅碳化硅半导体器件及其制造方法

    公开(公告)号：US20140001472A1

    公开(公告)日：2014-01-02

    申请号：US13995993

    申请日：2011-05-18

    申请人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Masayuki Imaizumi

    发明人： Akihiko Furukawa ,  Yasuhiro Kagawa ,  Naruhisa Miura ,  Masayuki Imaizumi

    IPC分类号： H01L29/16 ,  H01L21/02

    CPC分类号： H01L21/02529 ,  H01L21/8213 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/872

    摘要： A silicon carbide semiconductor device including an SBD measuring a temperature of a silicon carbide semiconductor element. The silicon carbide semiconductor device includes a MOSFET formed on a silicon carbide epitaxial substrate, and an SBD section measuring a temperature of the MOSFET. The SBD section includes an n-type cathode region in a surface portion of a silicon carbide drift layer; an anode titanium electrode formed on the cathode region, the electrode serving as a Schottky electrode; an n-type cathode contact region of a higher concentration than that of the cathode region, formed in the surface portion of the silicon carbide drift layer to make contact with the cathode region; a cathode ohmic electrode formed on the cathode contact region; and a first p-type well region formed within the silicon carbide drift layer to surround peripheries of the cathode region and the cathode contact region.

    摘要翻译： 一种碳化硅半导体器件，包括测量碳化硅半导体元件的温度的SBD。 碳化硅半导体器件包括形成在碳化硅外延衬底上的MOSFET和测量MOSFET的温度的SBD部分。 SBD部分包括在碳化硅漂移层的表面部分中的n型阴极区域; 在阴极区域形成的阳极钛电极，用作肖特基电极的电极; 形成在碳化硅漂移层的表面部分中以与阴极区接触的n型阴极接触区域，其浓度高于阴极区域; 形成在阴极接触区域上的阴极欧姆电极; 以及形成在碳化硅漂移层内以围绕阴极区域和阴极接触区域的周边的第一p型阱区域。

    Method for manufacturing silicon carbide semiconductor device
    5.
    发明授权
    Method for manufacturing silicon carbide semiconductor device 有权
    碳化硅半导体器件的制造方法

    公开(公告)号：US08367536B2

    公开(公告)日：2013-02-05

    申请号：US13319739

    申请日：2010-07-16

    申请人： Hiroshi Watanabe ,  Naruhisa Miura

    发明人： Hiroshi Watanabe ,  Naruhisa Miura

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068

    摘要： The present invention includes steps below: (a) forming, on a drift layer, a first ion implantation mask and a second ion implantation mask individually by photolithography to form a third ion implantation mask, the first ion implantation mask having a mask region corresponding to a channel region and having a first opening corresponding to a source region, the second ion implantation mask being positioned in contact with an outer edge of the first ion implantation mask and configured to form a base region; (b) implanting impurities of a first conductivity type from the first opening with an ion beam using the third ion implantation mask to form a source region in an upper layer part of the silicon carbide drift layer; (c) removing the first ion implantation mask after the formation of the source region; and (d) implanting impurities of a second conductivity type with an ion beam from a second opening formed in the second ion implantation mask after the removal of the first ion implantation mask to form a base region deeper than the source region in the upper layer part of the drift layer.

    摘要翻译： 本发明包括以下步骤：（a）通过光刻法分别在漂移层上形成第一离子注入掩模和第二离子注入掩模，以形成第三离子注入掩模，第一离子注入掩模具有对应于 沟道区，具有对应于源极区的第一开口，所述第二离子注入掩模定位成与所述第一离子注入掩模的外边缘接触并且被配置为形成基区; （b）使用第三离子注入掩模，用离子束从第一开口注入第一导电类型的杂质，以在碳化硅漂移层的上层部分中形成源极区; （c）在形成源极区域之后去除第一离子注入掩模; 以及（d）在除去第一离子注入掩模之后，从形成在第二离子注入掩模中的第二开口用离子束注入第二导电类型的杂质以形成比上层部分中的源极区更深的基极区 的漂移层。

    Semiconductor device and method of manufacturing the same
    6.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08222649B2

    公开(公告)日：2012-07-17

    申请号：US12161592

    申请日：2006-11-17

    申请人： Naruhisa Miura ,  Keiko Fujihira ,  Kenichi Otsuka ,  Masayuki Imaizumi

    发明人： Naruhisa Miura ,  Keiko Fujihira ,  Kenichi Otsuka ,  Masayuki Imaizumi

    IPC分类号： H01L29/161 ,  H01L29/167 ,  H01L21/36

    CPC分类号： H01L29/0661 ,  H01L29/0615 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/7811

    摘要： A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.

    摘要翻译： 一种半导体器件及其制造方法，用于适当地确定场释放区域的杂质浓度分布并降低导通电阻。 半导体器件包括衬底，第一漂移层，第二漂移层，第一阱区，第二阱区，电流控制区和场释放区。 第一阱区从与第二漂移层的外周部附近相邻的端部连续配置到第一漂移层的位于外周部附近的部分。 场解除区域被布置在第一漂移层中以与第一阱区域相邻。

    POWER SEMICONDUCTOR DEVICE
    7.
    发明申请
    POWER SEMICONDUCTOR DEVICE 审中-公开
    功率半导体器件

    公开(公告)号：US20120074508A1

    公开(公告)日：2012-03-29

    申请号：US13309305

    申请日：2011-12-01

    申请人： Kenichi OHTSUKA ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

    发明人： Kenichi OHTSUKA ,  Naruhisa Miura ,  Masayuki Imaizumi ,  Tatsuo Oomori

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/66068 ,  H01L29/7828

    摘要： A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer.

    摘要翻译： 功率半导体器件在其高温操作期间不容易引起用于互连的金属材料与连接到半导体区域的电极等之间的反应，并且在其高温操作期间不易于变形。 功率半导体器件可以是在形成在半导体区域上的源电极上形成含有选自Pt，Ti，Mo，W和Ta中的至少一种的第一金属层的SiC功率器件等， 例如源区域等。 在第一金属层上形成含有选自Mo，W和Cu中的至少一种的第二金属层。 在第二金属层上形成含有选自Pt，Mo和W中的至少一种的第三金属层。

    SILICON CARBIDE SEMICONDUCTOR DEVICE
    8.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
    硅碳化硅半导体器件

    公开(公告)号：US20110278599A1

    公开(公告)日：2011-11-17

    申请号：US13146812

    申请日：2010-02-23

    申请人： Yukiyasu Nakao ,  Masayuki Imaizumi ,  Shuhei Nakata ,  Naruhisa Miura

    发明人： Yukiyasu Nakao ,  Masayuki Imaizumi ,  Shuhei Nakata ,  Naruhisa Miura

    IPC分类号： H01L29/161

    CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7396 ,  H01L29/7811 ,  H01L29/7816

    摘要： A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.

    摘要翻译： 一种能够提高开关速度而不破坏栅极绝缘膜的SiC半导体器件。 此外，在由SiC构成的n型半导体基板的SiC-MOSFET中，p型半导体层全部或部分设置在p型阱层的上表面上，该p型阱层的横面为最大面积 在设置在n型漂移层中的多个p型阱层之中，并且布置在栅电极焊盘正下方的最外周。 p型半导体层中含有的杂质的浓度优选大于p型阱层的浓度。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06566734B2

    公开(公告)日：2003-05-20

    申请号：US09809211

    申请日：2001-03-16

    申请人： Kohei Sugihara ,  Toshiyuki Oishi ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    发明人： Kohei Sugihara ,  Toshiyuki Oishi ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    IPC分类号： H01L29788

    CPC分类号： H01L29/66651 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66621

    摘要： In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.

    摘要翻译： 在制作场效应晶体管时，在形成栅电极之前形成伪栅电极。 相对于虚拟栅电极形成延伸区域，侧壁氮化硅膜，源极/漏极区域，氧化硅膜等元件。 去除虚拟栅电极，并且去除扩散到虚拟栅电极正下方的区域中的一部分延伸区域。 被去除的部分填充硅选择外延膜。 之后，形成预定的栅电极。 该制造方法产生场效应晶体管，其防止由短沟道效应和寄生电阻引起的电特性的劣化。