公开(公告)号：US5812491A

公开(公告)日：1998-09-22

申请号：US916201

申请日：1997-08-22

申请人： Naoharu Shinozaki ,  Tatsuya Kanda

发明人： Naoharu Shinozaki ,  Tatsuya Kanda

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072

摘要： A mode register control circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.

摘要翻译： 一种用于半导体器件的模式寄存器控制电路包括：第一控制单元，用于使用用于指示闭锁电路被初始化的初始化信号来防止模式寄存器的内容，初始化在半导体器件之后发生的瞬变中完成 被打开 在第二控制单元中，即使在模式寄存器设置命令未被执行的情况下，指示模式寄存器也执行模式寄存器读取命令，条件是当半导体器件转动时检测到除模式寄存器读取命令之外的外部命令 上; 或第三控制单元，用于在半导体器件接通之后执行模式寄存器设置命令的条件来指示模式寄存器执行模式寄存器读取命令。

公开(公告)号：US5699302A

公开(公告)日：1997-12-16

申请号：US715701

申请日：1996-09-19

申请人： Naoharu Shinozaki ,  Tatsuya Kanda

发明人： Naoharu Shinozaki ,  Tatsuya Kanda

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072

摘要： A mode register control, circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.

摘要翻译： 模式寄存器控制，半导体器件的电路包括：第一控制单元，用于使用用于指示锁存电路被初始化的初始化信号来防止模式寄存器的内容，初始化在半导体之后发生的瞬变中进行 设备已打开; 在第二控制单元中，即使在模式寄存器设置命令未被执行的情况下，指示模式寄存器也执行模式寄存器读取命令，条件是当半导体器件转动时检测到除模式寄存器读取命令之外的外部命令 上; 或第三控制单元，用于在半导体器件接通之后执行模式寄存器设置命令的条件来指示模式寄存器执行模式寄存器读取命令。

公开(公告)号：US08077537B2

公开(公告)日：2011-12-13

申请号：US12612215

申请日：2009-11-04

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控​​制器及其存储器系统。 响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作， 并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作 在刷新目标银行。

公开(公告)号：US08004921B2

公开(公告)日：2011-08-23

申请号：US12612247

申请日：2009-11-04

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

公开(公告)号：US07814294B2

公开(公告)日：2010-10-12

申请号：US11698286

申请日：2007-01-26

申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G06F12/06

CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

公开(公告)号：US20100172200A1

公开(公告)日：2010-07-08

申请号：US12612247

申请日：2009-11-04

申请人： Tomohiro KAWAKUBO ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro KAWAKUBO ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控​​制器及其存储器系统。 响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作， 并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作 在刷新目标银行。

公开(公告)号：US07668040B2

公开(公告)日：2010-02-23

申请号：US11707252

申请日：2007-02-16

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/10

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

摘要翻译： 存储器件具有：多个存储体，每个存储体具有存储单元阵列，该存储单元阵列具有分别由行地址选择的多个页面区域，并且每个区域由银行地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址 提供的银行地址和提供的行地址。 响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

公开(公告)号：US20080151678A1

公开(公告)日：2008-06-26

申请号：US11707252

申请日：2007-02-16

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C8/12

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

摘要翻译： 存储器件具有：多个存储体，每个存储体具有分别由行地址选择的多个页面区域的存储单元阵列，并且每个存储单元阵列由存储体地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址 提供的银行地址和提供的行地址。 响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

公开(公告)号：US20080025127A1

公开(公告)日：2008-01-31

申请号：US11705405

申请日：2007-02-13

申请人： Tatsuya Kanda ,  Kotoku Sato

发明人： Tatsuya Kanda ,  Kotoku Sato

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4096

摘要： To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.

摘要翻译： 即使当数据屏蔽信号中的位数较大时，即使在数据屏蔽信号中的位数较大的情况下，也可以不增加外部端子的数量来执行数据信号的屏蔽控制，地址输入电路顺序地接收第一地址信号，第二地址信号和第一数据屏蔽信号 与时钟信号的过渡沿同步地提供给地址终端。 即，第一数据屏蔽信号以与接收第一和第二地址信号的定时不同的定时提供给地址终端。 例如，第一地址信号，第二地址信号和第一数据掩码信号从访问半导体存储器的控制器输出。 数据输入/输出电路通过数据端口输入/输出数据，并根据第一数据屏蔽信号的逻辑，将写数据中的至少一个写入存储单元并从存储单元读取数据。

公开(公告)号：US20050105372A1

公开(公告)日：2005-05-19

申请号：US10788380

申请日：2004-03-01

申请人： Tatsuya Kanda

发明人： Tatsuya Kanda

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C2207/2227

摘要： A boost voltage generator generates a boost voltage as a high-level voltage of word lines. First word decoders output a low-level voltage or the high-level voltage according to a first address signal in an active period, and outputs the high-level voltage in a standby period. A switch circuit connects a high-level voltage line for supplying the high-level voltage to the first word decoders, with a boost voltage line in the active period, and connects the same with an internal voltage line in the standby period. The internal voltage line is supplied with a voltage lower than the boost voltage. Word drivers supply the boost voltage to the word lines when the gates of their transistors receive the low-level voltage from the first word decoders, and output the low-level voltage to the word lines when the gates thereof receive the high-level voltage from the first word decoders.