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    Temperature determination and communication for multiple devices of a memory module
    31.
    发明申请
    Temperature determination and communication for multiple devices of a memory module 有权
    存储器模块的多个器件的温度测定和通信

    公开(公告)号：US20060221741A1

    公开(公告)日：2006-10-05

    申请号：US11093905

    申请日：2005-03-30

    Applicant: Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

    Inventor： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

    IPC: G11C7/04

    CPC classification number: G11C5/04 ,  G01K7/425 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1063 ,  G11C11/40626 ,  G11C29/028 ,  G11C2029/5002

    Abstract: Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

    Abstract translation: 在包含多个存储器件的存储器模块的上下文中描述了热管理和通信。 在一个示例中，本发明包括确定第一存储器件的温度，第一存储器件包含多个存储器单元，在确定第一存储器件的温度之后确定第二存储器件的温度，第二存储器器件包含 多个存储单元，并且基于第一和第二温度的评估来产生报警。 在另一个示例中，本发明包括检测包含多个存储器件的存储器模块的存储器件上的热事件，检测存储器模块的事件总线的状态，以及如果事件发生在事件总线上的警报 公共汽车处于空闲状态。

    Self-terminated driver to prevent signal reflections of transmissions between electronic devices
    32.
    发明授权
    Self-terminated driver to prevent signal reflections of transmissions between electronic devices 有权
    自终端驱动器，以防止电子设备之间传输的信号反射

    公开(公告)号：US06369605B1

    公开(公告)日：2002-04-09

    申请号：US09664994

    申请日：2000-09-18

    Applicant: Randy Bonella ,  John Halbert

    Inventor： Randy Bonella ,  John Halbert

    IPC: H03K1716

    CPC classification number: H03K19/018585

    Abstract: An output driver circuit within an electronic device to provide a configurable driver circuit. When placed in a first mode of operation, the driver circuit drives an output signal. When placed in a second mode of operation, the driver circuit provides impedance matching to prevent signal reflection.

    Abstract translation: 电子设备内的输出驱动器电路，用于提供可配置的驱动电路。 当处于第一操作模式时，驱动器电路驱动输出信号。 当处于第二操作模式时，驱动电路提供阻抗匹配以防止信号反射。

    Common memory device for variable device width and scalable pre-fetch and page size
    33.
    发明授权
    Common memory device for variable device width and scalable pre-fetch and page size 有权
    用于可变设备宽度和可扩展预取和页面大小的通用存储设备

    公开(公告)号：US08238189B2

    公开(公告)日：2012-08-07

    申请号：US13096137

    申请日：2011-04-28

    Applicant: Kuljit S. Bains ,  John Halbert

    Inventor： Kuljit S. Bains ,  John Halbert

    IPC: G11C8/00

    CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

    Abstract translation: 本发明的实施例通常涉及用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器件（例如DRAM）可以以包括例如×4模式，×8模式和×16模式在内的多种模式中的任何一种工作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也根据DRAM的模式而变化。

    COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE
    34.
    发明申请
    COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE 有权
    用于可变器件宽度和可扩展前置电流和页面大小的通用存储器件

    公开(公告)号：US20110261636A1

    公开(公告)日：2011-10-27

    申请号：US13096137

    申请日：2011-04-28

    Applicant: Kuljit S. Bains ,  John Halbert

    Inventor： Kuljit S. Bains ,  John Halbert

    IPC: G11C8/18

    CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a ×4 mode, a ×8 mode, and a ×16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

    Abstract translation: 本发明的实施例通常涉及用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器件（例如DRAM）可以以包括例如×4模式，×8模式和×16模式在内的多种模式中的任何一种工作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也根据DRAM的模式而变化。

    High speed DRAM cache architecture
    36.
    发明授权
    High speed DRAM cache architecture 有权
    高速DRAM缓存架构

    公开(公告)号：US07350016B2

    公开(公告)日：2008-03-25

    申请号：US11329994

    申请日：2006-01-10

    Applicant: Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    Inventor： Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0882

    Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

    Abstract translation: 高速DRAM缓存架构。 一个公开的实施例包括与多路复用总线接口的多路复用总线接口。 高速缓存控制电路驱动复用总线接口上的地址的行地址部分，以及打开包含多路数据的存储器页的命令。 高速缓存控制电路随后将包括至少一路指示符的列地址驱动到多路复用的总线接口。

    Method, apparatus, and system for active refresh management
    37.
    发明申请
    Method, apparatus, and system for active refresh management 有权
    用于主动刷新管理的方法，装置和系统

    公开(公告)号：US20060133173A1

    公开(公告)日：2006-06-22

    申请号：US11019881

    申请日：2004-12-21

    Applicant: Sandeep Jain ,  Animesh Mishra ,  John Halbert

    Inventor： Sandeep Jain ,  Animesh Mishra ,  John Halbert

    IPC: G11C7/00

    CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622

    Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

    Abstract translation: 一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数 ，从而减少刷新期间消耗的功率量。

    High speed DRAM cache architecture
    38.
    发明授权
    High speed DRAM cache architecture 有权
    高速DRAM缓存架构

    公开(公告)号：US07054999B2

    公开(公告)日：2006-05-30

    申请号：US10210908

    申请日：2002-08-02

    Applicant: Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    Inventor： Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0882

    Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

    Abstract translation: 高速DRAM缓存架构。 一个公开的实施例包括与多路复用总线接口的多路复用总线接口。 高速缓存控制电路驱动复用总线接口上的地址的行地址部分，以及打开包含多路数据的存储器页的命令。 高速缓存控制电路随后将包括至少一路指示符的列地址驱动到多路复用总线接口。

    Memory module and memory component built-in self test
    39.
    发明授权
    Memory module and memory component built-in self test 有权
    内存模块和内存组件内置自检

    公开(公告)号：US06928593B1

    公开(公告)日：2005-08-09

    申请号：US09664910

    申请日：2000-09-18

    Applicant: John Halbert ,  Randy M. Bonella

    Inventor： John Halbert ,  Randy M. Bonella

    IPC: G11C29/14 ,  G11C29/00

    CPC classification number: G11C29/12015 ,  G11C11/401 ,  G11C29/14 ,  G11C2029/0405

    Abstract: A memory component with built-in self test includes a memory array. An input/output interface is coupled to the memory array and has a loopback. A controller is provided to transmit memory array test data to the memory array to store the memory array test data, and to read the memory array test data from the memory array. A compare register is also provided to compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array.

    Abstract translation: 具有内置自检功能的内存组件包括一个内存阵列。 输入/输出接口耦合到存储器阵列并具有环回。 提供控制器将存储器阵列测试数据发送到存储器阵列以存储存储器阵列测试数据，并从存储器阵列读取存储器阵列测试数据。 还提供了比较寄存器，用于将发送到存储器阵列的存储器阵列测试数据与从存储器阵列读取的存储器阵列测试数据进行比较。

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