RECONSTRUCTION OF SPARSE DATA
    31.
    发明申请
    RECONSTRUCTION OF SPARSE DATA 有权
    重新建立稀疏数据

    公开(公告)号:US20120134597A1

    公开(公告)日:2012-05-31

    申请号:US12954843

    申请日:2010-11-26

    IPC分类号: G06K9/46

    CPC分类号: G06T17/00 G06T7/50

    摘要: A dense guide image or signal is used to inform the reconstruction of a target image from a sparse set of target points. The guide image and the set of target points are assumed to be derived from a same real world subject or scene. Potential discontinuities (e.g., tears, edges, gaps, etc.) are first detected in the guide image. The potential discontinuities may be borders of Voronoi regions, perhaps computed using a distance in data space (e.g., color space). The discontinuities and sparse set of points are used to reconstruct the target image. Specifically, pixels of the target image may be interpolated smoothly between neighboring target points, but where neighboring target points are separated by a discontinuity, the interpolation may jump abruptly (e.g., by adjusting or influencing relaxation) at the discontinuity. The target points may be used to select only a subset of the discontinuities to be used during reconstruction.

    摘要翻译: 使用密集的引导图像或信号来通知来自稀疏目标点集合的目标图像的重建。 引导图像和目标点集合被假定为从相同的现实主题或场景导出。 在引导图像中首先检测到潜在的不连续性(例如,泪液,边缘,间隙等)。 潜在的不连续性可以是Voronoi区域的边界,可以使用数据空间中的距离(例如,颜色空间)来计算。 不连续点和稀疏集合点用于重建目标图像。 具体地说,目标图像的像素可以在相邻目标点之间平滑地内插,但是当相邻目标点被不连续性分开时,插值可能突然地跳跃(例如通过调节或影响松弛)而跳跃。 目标点可以用于仅在重建期间仅选择要使用的不连续的子集。

    SILICON THIN FILM TRANSISTORS, SYSTEMS, AND METHODS OF MAKING SAME

    公开(公告)号:US20090191670A1

    公开(公告)日:2009-07-30

    申请号:US12359929

    申请日:2009-01-26

    IPC分类号: H01L21/84

    摘要: Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures such that the precision, resolution, and registration is achieved to produce a high performing transistor. Such TFTs can be used in applications such as displays, packaging, labeling, and the like.

    Multi-chart geometry images
    33.
    发明申请
    Multi-chart geometry images 有权
    多图几何图像

    公开(公告)号:US20070296719A1

    公开(公告)日:2007-12-27

    申请号:US11895179

    申请日:2007-08-23

    IPC分类号: G06T15/10

    CPC分类号: G06T17/20

    摘要: Techniques and tools for mesh processing are described. For example, a multi-chart geometry image represents arbitrary surfaces on object models. The multi-chart geometry image is created by resampling a surface onto a regular 2D grid, using a flexible atlas construction to map the surface piecewise onto charts of arbitrary shape. This added flexibility reduces parameterization distortion and thus provides greater geometric fidelity, particularly for shapes with long extremities, high genus, or disconnected components. As another example, zippering creates a watertight surface on reconstructed triangle meshes. The zippering unifies discrete paths of samples along chart boundaries to form the watertight mesh.

    摘要翻译: 描述了网格处理的技术和工具。 例如,多图几何图形表示对象模型上的任意曲面。 多图几何图像是通过将表面重新采样到普通2 D格网上创建的,使用灵活的地图集结构将表面分段映射到任意形状的图表上。 这种增加的灵活性降低了参数化失真,从而提供更大的几何保真度,特别是对于具有长末端,高类别或断开组件的形状。 作为另一个例子,拉链在重建的三角形网格上形成水密表面。 拉链将样本的离散路径与图表边界统一起来形成水密网格。

    Metal source/drain Schottky barrier silicon-on-nothing MOSFET device and method thereof
    35.
    发明申请
    Metal source/drain Schottky barrier silicon-on-nothing MOSFET device and method thereof 审中-公开
    金属源/漏肖特基势垒无硅MOSFET器件及其方法

    公开(公告)号:US20070194353A1

    公开(公告)日:2007-08-23

    申请号:US11513894

    申请日:2006-08-31

    申请人: John Snyder

    发明人: John Snyder

    IPC分类号: H01L31/112 H01L21/338

    摘要: A Schottky barrier MOSFET (SB-MOS) device and a method of manufacturing having a silicon-on-nothing (SON) architecture in a channel region is provided. More specifically, metal source/drain SB-MOS devices are provided in combination with a channel structure comprising a semiconductor channel region such as silicon isolated from a bulk substrate by an SON dielectric layer. In one embodiment, the SON dielectric layer has a triple stack structure comprising oxide on nitride on oxide, which is in contact with the underlying semiconductor substrate.

    摘要翻译: 提供了肖特基势垒MOSFET(SB-MOS)器件及其在沟道区中具有无硅无结构(SON)结构的制造方法。 更具体地,金属源极/漏极SB-MOS器件与包括半导体沟道区(例如通过SON介电层从体衬底隔离的硅)的沟道结构组合提供。 在一个实施例中,SON介电层具有三重堆叠结构,其包含与氧化物上的氧化物,其与下面的半导体衬底接触。

    CMOS device with zero soft error rate
    36.
    发明申请
    CMOS device with zero soft error rate 有权
    具有零软错误率的CMOS器件

    公开(公告)号:US20070080406A1

    公开(公告)日:2007-04-12

    申请号:US11546829

    申请日:2006-10-12

    IPC分类号: H01L29/94

    摘要: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

    摘要翻译: 提供了一种CMOS器件和制造方法,用于产生不易受各种软错误(例如单事件颠簸,多位异常或单事件闭锁)的集成电路的影响。 CMOS器件和方法利用新的和新颖的结构与金属源极/漏电极的结构,以消除软错误。 在一个实施例中,CMOS器件使用用于NMOS器件的第一金属源/漏极材料和用于PMOS器件的第二金属源极/漏极材料。 CMOS器件还使用具有用于PMOS器件的浅N阱和掩埋P阱的多层阱结构以及用于NMOS器件的浅P阱和掩埋N阱。

    Multi-chart geometry images
    38.
    发明申请
    Multi-chart geometry images 有权
    多图几何图像

    公开(公告)号:US20050151733A1

    公开(公告)日:2005-07-14

    申请号:US10755206

    申请日:2004-01-09

    IPC分类号: G06T17/20

    CPC分类号: G06T17/20

    摘要: Techniques and tools for mesh processing are described. For example, a multi-chart geometry image represents arbitrary surfaces on object models. The multi-chart geometry image is created by resampling a surface onto a regular 2D grid, using a flexible atlas construction to map the surface piecewise onto charts of arbitrary shape. This added flexibility reduces parameterization distortion and thus provides greater geometric fidelity, particularly for shapes with long extremities, high genus, or disconnected components. As another example, zippering creates a watertight surface on reconstructed triangle meshes. The zippering unifies discrete paths of samples along chart boundaries to form the watertight mesh.

    摘要翻译: 描述了网格处理的技术和工具。 例如,多图几何图形表示对象模型上的任意曲面。 多图几何图像是通过将表面重新采样到常规2D网格上,使用灵活的图谱结构将表面分段映射到任意形状的图表上创建的。 这种增加的灵活性降低了参数化失真,从而提供更大的几何保真度,特别是对于具有长末端,高类别或断开组件的形状。 作为另一个例子,拉链在重建的三角形网格上形成水密表面。 拉链将样本的离散路径与图表边界统一起来形成水密网格。

    Dynamic schottky barrier MOSFET device and method of manufacture
    39.
    发明申请
    Dynamic schottky barrier MOSFET device and method of manufacture 审中-公开
    动态肖特基势垒MOSFET器件及其制造方法

    公开(公告)号:US20050139860A1

    公开(公告)日:2005-06-30

    申请号:US10970688

    申请日:2004-10-21

    摘要: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

    摘要翻译: 提供一种用于调节电流流动的装置及其制造方法。 该器件包括形成肖特基势垒或肖特基状结到半导体衬底的金属 - 绝缘体 - 半导体源极 - 漏极接触。 该器件包括在半导体衬底和金属源极和/或漏极之间的界面层,从而通过施加不同的偏置条件来动态地调节肖特基势垒高度。 动态肖特基势垒调制为低漏极偏置条件提供了增加的电流,降低了肖特基势垒MOSFET器件的亚线性导通特性并提高器件性能。

    Systems and methods for optimizing geometric stretch of a parametrization scheme
    40.
    发明申请
    Systems and methods for optimizing geometric stretch of a parametrization scheme 有权
    用于优化参数化方案的几何拉伸的系统和方法

    公开(公告)号:US20050088438A1

    公开(公告)日:2005-04-28

    申请号:US10978098

    申请日:2004-10-29

    IPC分类号: G06T17/20 G06T17/00

    CPC分类号: G06T17/20

    摘要: Systems and methods are provided for optimizing the geometric stretch of a parametrization scheme. Given an arbitrary mesh, the systems and methods construct a progressive mesh (PM) such that all meshes in the PM sequence share a common texture parametrization. The systems and methods minimize geometric stretch, i.e., small texture distances mapped onto large surface distances, to balance sampling rates over all locations and directions on the surface. The systems and methods also minimize texture deviation, i.e., “slippage” error based on parametric correspondence, to obtain accurate textured mesh approximations. The technique(s) begin by partitioning the mesh into charts using planarity and compactness heuristics. Then, the technique(s) proceed by creating a stretch-minimizing parametrization within each chart, and by resizing the charts based on the resulting stretch. Then, the technique(s) simplify the mesh while respecting the chart boundaries. Next, the parametrization is re-optimized to reduce both stretch and deviation over the whole PM sequence. The charts may then be packed into a texture atlas for improved texture mapping in connection with a parametrization scheme.

    摘要翻译: 提供了用于优化参数化方案的几何拉伸的系统和方法。 给定任意网格,系统和方法构造渐进网格(PM),使得PM序列中的所有网格共享共同的纹理参数化。 系统和方法使几何拉伸最小化,即映射到大表面距离上的小纹理距离,以平衡表面上所有位置和方向上的采样率。 系统和方法还使纹理偏差最小化,即基于参数对应的“滑移”误差,以获得精确的纹理网格近似。 该技术首先将网格划分为使用平面性和紧凑性启发式的图表。 然后,通过在每个图表内创建拉伸最小化参数化,并且基于所得的拉伸来调整图表大小来继续进行该技术。 然后,技术简化网格,同时遵循图表边界。 接下来,参数化被重新优化以减少整个PM序列的拉伸和偏差。 然后可以将图表打包到纹理图集中,以改进与参数化方案相关的纹理映射。