公开(公告)号：US20060073232A1

公开(公告)日：2006-04-06

申请号：US10905802

申请日：2005-01-21

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: B29D11/00

CPC classification number: B29C43/021 ,  B29C33/303 ,  B29C43/36 ,  B29C2043/3618 ,  B29D11/00413 ,  B29L2011/0016 ,  C03B11/08 ,  C03B2215/03 ,  C03B2215/60 ,  C03B2215/65 ,  C03B2215/72 ,  Y10S425/808 ,  Y10S425/812

Abstract: An optical lens molding apparatus includes a cylindrical mold, a first mold core, a second mold core and a correctional ring. The first and the second mold core have a columnar shape and are disposed inside the cylindrical mold to form a cavity. Furthermore, the first and the second mold core have a planar portion at the end surface facing the cavity. The correctional ring is disposed on the planar portion of the second mold core. The correction ring corrects any face tilting of the molded optical lens due to the tilting of the first mold core. The present invention also provides a precision molding apparatus for forming precision parts.

Abstract translation: 光学透镜成型装置包括圆柱形模具，第一模芯，第二模芯和校正环。 第一和第二模芯具有圆柱形状并且设置在圆柱形模具内以形成空腔。 此外，第一和第二模芯在端面处具有面向空腔的平面部分。 校正环设置在第二模芯的平面部分上。 由于第一模芯的倾斜，校正环校正模制的光学透镜的任何表面倾斜。 本发明还提供一种用于形成精密部件的精密成形装置。

公开(公告)号：US20060048544A1

公开(公告)日：2006-03-09

申请号：US11151877

申请日：2005-06-13

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: C03B11/08

CPC classification number: C23C16/30 ,  C03B11/086 ,  C03B2215/12 ,  C03B2215/24 ,  C03B2215/31 ,  C03B2215/34 ,  C23C16/0272

Abstract: A molding core includes: a core body having an article-shaping surface; and a hard coating formed on the article-shaping surface of the core body and including a diamond-like carbon film that includes carbon, oxygen, and at least one bonding-enhancing element which is selected from silicon, titanium, aluminum, tungsten, tantalum, chromium, zirconium, vanadium, niobium, hafnium, and boron, and which forms covalence bonding with the carbon and the oxygen.

Abstract translation: 成形芯包括：具有制品成形表面的芯体; 以及形成在芯体的制品成形表面上的硬涂层，并且包括包含碳，氧和至少一种选自硅，钛，铝，钨，钽的粘合增强元素的类金刚石碳膜 ，铬，锆，钒，铌，铪和硼，并且与碳和氧键合形成共价。

公开(公告)号：US20050150253A1

公开(公告)日：2005-07-14

申请号：US11011130

申请日：2004-12-15

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: C03B11/08 ,  C03B27/02 ,  C03B35/00 ,  C03C17/00

CPC classification number: C03C17/001 ,  C03B11/086 ,  C03B27/02 ,  C03C2218/15 ,  Y02P40/57

Abstract: A method for making high precision hard film coating on a mold core comprises the following steps of: (a) providing a mold jig (200, 300) and a mold core (208, 308); (b) defining a through hole (206, 364) of a first inner diameter in the mold jig; (c) forming a rim (254, 354) of a second inner diameter on the inner side of the through hole, the second inner diameter being smaller than the first inner diameter; (d) configuring the mold core into a mold core including a body (212, 312) of a first external diameter and a top portion (250, 350) of a second external diameter, the second external diameter being smaller than the first external diameter to define a shoulder (252, 352) between the body and the top portion, the first external diameter being substantially equal to the first inner diameter and larger than the second inner diameter, the second external diameter being substantially equal to or smaller than the second inner diameter; and (e) coreing the mold core into the through hole of the mold jig from the bottom, the shoulder of the mold core engaging with the rim, the upper surface of the top portion of the mold core being substantially flush with the upper surface of the mold jig, and a groove (256, 356) being defined between the inner side of the through hole and the outer side of the top portion of the mold core. A device for performing this method is also disclosed.

Abstract translation: 在模芯上制造高精度硬膜的方法包括以下步骤：（a）提供模具夹具（200,300）和模芯（208,308）; （b）在所述模具夹具中限定第一内径的通孔（206,364）; （c）在所述通孔的内侧上形成第二内径的边缘（254,354），所述第二内径小于所述第一内径; （d）将模芯配置成包括第一外径的主体（212,312）和第二外径的顶部（250,350）的模芯，所述第二外径小于所述第一外径 以限定主体和顶部之间的肩部（252,352），第一外径基本上等于第一内径并且大于第二内径，第二外径基本上等于或小于第二内径 内径; 和（e）将模芯从底部夹入模具夹具的通孔中，模芯的凸缘与边缘接合，模芯顶部的上表面基本上与 模具夹具和在通孔的内侧和模芯的顶部的外侧之间限定的凹槽（256,356）。 还公开了一种用于执行该方法的装置。

公开(公告)号：US06707129B2

公开(公告)日：2004-03-16

申请号：US10020311

申请日：2001-12-18

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: H01L2900

CPC classification number: H01L23/5329 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure for using fuse structure integrated wire bonding on the substrate, and relates to methods for making the same are disclosed, in which an Al-fuse has an extra-etching process pattern by fuse-open mask and has been thinned down from Al-fuse thickness. The Al fuse structure integrated Al wire-bonding pad has two kind of thickness under fuse-open and for the other area. This invention makes the fuse easy to blow without suffering any bondability from wire bonding for packaging.

Abstract translation: 公开了一种用于在基板上使用熔丝结构集成引线接合的结构，并且涉及其制造方法，其中Al熔丝具有通过熔断器开口掩模的额外蚀刻工艺图案，并且已经从Al- 保险丝厚度。 Al熔丝结构集成铝线焊盘在熔断器开放和其他区域具有两种厚度。 本发明使得熔断器容易吹塑，而不会因包装引线接合而受到任何粘结。

公开(公告)号：US06371045B1

公开(公告)日：2002-04-16

申请号：US09360627

申请日：1999-07-26

Applicant: Kun-Chih Wang ,  Chao-Ching Hsieh

Inventor： Kun-Chih Wang ,  Chao-Ching Hsieh

IPC: C23C1600

CPC classification number: H01J37/3266 ,  C23C14/046 ,  C23C14/165 ,  C23C14/351 ,  C23C14/358 ,  H01J37/34

Abstract: The present invention provides a physical vapor deposition device for forming a metallic layer with a predetermined thickness on a semiconductor wafer. The PVD device comprises a chamber, a wafer chuck installed at the bottom end of the chamber through which the semiconductor wafer is hold horizontally, a metallic ion generator for generating metallic ions, an electric field generator for forming a vertical electric field above the wafer chuck that guides the metallic ions toward the wafer chuck, and a magnetic field generator. The magnetic field generator generates a magnetic field perpendicular to the direction of movement of the metallic ions to create a horizontal moving force on the metallic ions thus causing the metallic ions to deposit on the semiconductor wafer at a slant angle.

Abstract translation: 本发明提供一种用于在半导体晶片上形成具有预定厚度的金属层的物理气相沉积装置。 PVD装置包括一个室，安装在室底部的晶片卡盘，半导体晶片通过该底座水平保持，用于产生金属离子的金属离子发生器，用于在晶片卡盘上方形成垂直电场的电场发生器 其将金属离子引向晶片卡盘，以及磁场发生器。 磁场发生器产生垂直于金属离子移动方向的磁场，以在金属离子上产生水平移动力，从而使金属离子以倾斜角沉积在半导体晶片上。

公开(公告)号：US06180484B2

公开(公告)日：2001-01-30

申请号：US09140776

申请日：1998-08-26

Applicant: Kun-Chih Wang ,  Wen-Yi Hsieh

Inventor： Kun-Chih Wang ,  Wen-Yi Hsieh

IPC: H01L2120

CPC classification number: H01L28/60 ,  C23C16/14 ,  C23C16/56 ,  H01L21/7684 ,  H01L21/76877

Abstract: The present invention proposes a method for forming a tungsten film with a good surface property and utilizes a chemical plasma treatment to round the tungsten surface and to improve the leakage issue of tungsten conductive film. A fabrication of a DRAM cell capacitor with tungsten bottom electrode is described for a preferred embodiment. Forming an inter-layer dielectric on a semiconductor substrate, a tungsten layer is formed thereon. A chemical plasma treatment is carried out to round the tungsten surface spires and result in a better surface properties. The tungsten layer is patterned to serve as the bottom electrode, and another dielectric layer is formed to cover the bottom electrode of tungsten. Finally, the top storage electrode is formed to finish the present process.

Abstract translation: 本发明提出了一种形成具有良好表面性能的钨膜的方法，并利用化学等离子体处理使钨表面圆弧化并改善了钨导电膜的泄漏问题。 对于优选实施例描述了具有钨底电极的DRAM单元电容器的制造。 在半导体衬底上形成层间电介质，在其上形成钨层。 进行化学等离子体处理以使钨表面尖锐化，并产生更好的表面性能。 图案化钨层用作底部电极，并且形成另一个电介质层以覆盖钨的底部电极。 最后，形成顶部存储电极以完成本工艺。

公开(公告)号：US06169028A

公开(公告)日：2001-01-02

申请号：US09237787

申请日：1999-01-26

Applicant: Kun-Chih Wang ,  Ming-Sheng Yang ,  Wen-Yi Hsieh

Inventor： Kun-Chih Wang ,  Ming-Sheng Yang ,  Wen-Yi Hsieh

IPC: H10L2144

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76807

Abstract: A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.

Abstract translation: 一种制造金属互连结构的方法。 提供了包括其中的导电层的半导体衬底。 在半导体衬底上形成电介质层。 去除介电层的一部分以在其中形成双镶嵌开口和沟槽，其中双镶嵌开口暴露导电层。 沟槽大于双镶嵌开口。 在电介质层上形成保形阻挡层。 在阻挡层上形成保形金属层以填充双镶嵌开口并部分填充沟槽。 定位在沟槽中的金属层的厚度等于沟槽的深度。 在金属层上形成共形盖层。 执行CMP处理以去除沟槽外部的覆盖层，金属层和阻挡层，并且在双镶嵌开口外部。

公开(公告)号：US6080660A

公开(公告)日：2000-06-27

申请号：US32682

申请日：1998-02-27

Applicant: Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/31116 ,  H01L21/76802 ,  H01L21/76805

Abstract: A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

Abstract translation: 一种用于制造通孔结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上形成导电线和电介质层。 接下来，进行光刻和第一蚀刻操作，从而形成暴露导电线表面的电介质层中的开口。 第一蚀刻操作使用多种蚀刻剂，包括具有最高浓度的氟代丁烷。 由于在开口的底部存在再入口结构，因此进行第二蚀刻操作。 在第二蚀刻操作中，导电线的一部分被蚀刻固定的时间间隔以控制蚀刻程度。 因此，在开口的底部形成倾斜表面，并且消除了再入口结构。 在平坦化的底部，随后沉积材料的阶梯覆盖率增加。

公开(公告)号：US6013579A

公开(公告)日：2000-01-11

申请号：US176385

申请日：1998-10-21

Applicant: Kun-Chih Wang ,  Tri-Rung Yew

Inventor： Kun-Chih Wang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L21/00

CPC classification number: H01L21/76829 ,  H01L21/76802 ,  H01L21/76897

Abstract: A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.

Abstract translation: 用于防止通路中毒的自对准通孔工艺包括在基板上和预成型的金属层上形成氢倍半硅氧烷层，在氢倍半硅氧烷层上形成蚀刻停止层，在蚀刻停止层上形成氧化物层， 然后进行两步蚀刻工艺以形成通孔。 两步蚀刻工艺首先使用图案化的光致抗蚀剂层作为掩模对氧化物层进行图案化，然后使用图案化氧化物层作为掩模，将蚀刻停止层与氢倍半硅氧烷层一起图案化。 因为蚀刻停止层防止在光致抗蚀剂层去除过程中氢倍半硅氧烷层与氧等离子体反应，消除了中毒。

公开(公告)号：US5976984A

公开(公告)日：1999-11-02

申请号：US1416

申请日：1997-12-30

Applicant: Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

Inventor： Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L2924/0002

Abstract: A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.

Abstract translation: 公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。 该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。 然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。 光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。 然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。 然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。