公开(公告)号：US20060022195A1

公开(公告)日：2006-02-02

申请号：US10710761

申请日：2004-08-01

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: H01L23/58

CPC classification number: H01L22/32 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a scribe line structure, which includes a substrate, a plurality of dielectric layers of low dielectric constant materials formed on the substrate, at least a process monitor pattern made of materials of metal formed between the dielectric layers, and a dummy metal structure connected to the process monitor pattern. The dummy metal structure includes a plurality of dummy metal layers and a plurality of dummy vias. The dummy metal structure is formed on the surface of the substrate and is exposed in the region of the scribe line, thus facilitating heat dissipation and energy release from the scribe line structure.

Abstract translation: 本发明提供一种划片线结构，其包括基板，形成在基板上的多个低介电常数材料的电介质层，至少由形成在电介质层之间的金属材料制成的工艺监视图案，以及虚设金属 结构连接到过程监控模式。 虚拟金属结构包括多个虚拟金属层和多个虚拟通孔。 虚设金属结构形成在基板的表面上，并且在划线的区域中露出，从而有利于散热和从划线结构释放能量。

公开(公告)号：US06710448B2

公开(公告)日：2004-03-23

申请号：US09880518

申请日：2001-06-12

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: H01L2940

CPC classification number: H01L24/05 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

Abstract: A bonding pad structure. The bonding pad structure includes independently built current conduction structure and mechanical support structure between a bonding pad layer and a substrate. The current conduction structure is constructed using a plurality of serially connected conductive metallic layers each at a different height between the bonding pad layer and the substrate. The conductive metallic layers connect with each other via a plurality of plugs. At least one of the conductive metallic layers connects electrically with a portion of the device in the substrate by a signal conduction line. The mechanical support structure is constructed using a plurality of serially connected supportive metallic layers each at a different height between the bonding pad layer and the substrate. The supportive metallic layers connect with each other via a plurality of plugs. Furthermore, the mechanical support structure connects with a non-device section of the substrate so that stresses on the bonding pads are distributed evenly through the substrate.

Abstract translation: 焊盘结构。 焊盘结构包括独立构建的导电结构和在焊盘层和衬底之间的机械支撑结构。 电流传导结构使用在接合焊盘层和衬底之间的不同高度上的多个串联连接的导电金属层来构造。 导电金属层通过多个插头彼此连接。 至少一个导电金属层通过信号传导线与衬底中的器件的一部分电连接。 机械支撑结构使用多个串联连接的支撑金属层来构造，每个支撑金属层在接合焊盘层和衬底之间的不同高度处。 支撑金属层通过多个插头彼此连接。 此外，机械支撑结构与衬底的非器件部分连接，使得焊盘上的应力均匀地分布在衬底上。

公开(公告)号：US06245380B1

公开(公告)日：2001-06-12

申请号：US09249582

申请日：1999-02-11

Applicant: Shih-Wei Sun ,  Wen-Yi Hsieh ,  Water Lur ,  Kun-Chih Wang

Inventor： Shih-Wei Sun ,  Wen-Yi Hsieh ,  Water Lur ,  Kun-Chih Wang

IPC: B05D512

CPC classification number: H01L24/05 ,  H01L21/76807 ,  H01L21/76847 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.

Abstract translation: 通过在所提供的金属间介电层上形成保形阻挡层，开始形成焊盘的方法。 在阻挡层上形成第一金属层以部分地填充沟槽。 在第一金属层上形成薄胶层。 在胶层上形成第二金属层以填充沟槽。 部分去除第二金属层，胶层，第一金属层和阻挡层，以露出介质层。 因此在沟槽中形成接合焊盘结构。 焊盘结构包括第一金属焊盘和第二金属焊盘。

公开(公告)号：US6046097A

公开(公告)日：2000-04-04

申请号：US274599

申请日：1999-03-23

Applicant: Kevin Hsieh ,  Kun-Chih Wang ,  Wen-Yi Hsieh

Inventor： Kevin Hsieh ,  Kun-Chih Wang ,  Wen-Yi Hsieh

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76843

Abstract: A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto the substrate, wherein the direction of the first deposition is about vertical to the surface of the substrate, and therefore the bottom of the contact holes is then substantially deposited with the conductive material. Next, the chuck is secondly adjusted so that it has a tilt angle between the direction of the second deposition and rotation axis of the chuck. Finally, the chuck is continuously rotated and the conductive material is secondly deposited onto the substrate, and therefore the sidewall of the contact holes is then substantially deposited with the conductive material.

Abstract translation: 公开了一种用于改善接触孔的台阶覆盖的沉积方法。 该方法包括最初将半导体衬底放置在室的卡盘上，其中衬底具有一些接触孔。 首先调整卡盘，并且首先将导电材料沉积到基底上，其中第一沉积的方向大约垂直于基底的表面，因此接触孔的底部然后基本上沉积有导电材料。 接下来，卡盘被二次调节，使得其在第二沉积的方向和卡盘的旋转轴线之间具有倾斜角。 最后，卡盘连续旋转，导电材料第二次沉积在基片上，因此接触孔的侧壁然后基本上沉积有导电材料。

公开(公告)号：US20060226547A1

公开(公告)日：2006-10-12

申请号：US11422330

申请日：2006-06-06

Applicant: Kun-Chih Wang ,  Bing-Chang Wu

Inventor： Kun-Chih Wang ,  Bing-Chang Wu

IPC: H01L23/52

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10T428/24917 ,  Y10T428/265 ,  H01L2924/00014

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

Abstract translation: 强化焊盘结构包括限定在应力缓冲电介质层上的可粘合金属层和在应力缓冲介质层下设置的第一金属间电介质（IMD）层中的中间金属层。 中间金属层位于可接合的金属层的正下方，并且与可结合金属层电连接，多个通孔与可结合的金属层集成。 在第一IMD层下面的第二IMD层中金属框架被镶嵌。 金属框架直接位于中间金属层的正下方，用于抵抗在接合期间施加在可接合金属层上的机械应力，当所述应力缓冲介电层的厚度大于2000埃时，可以省略镶嵌的金属框架。 包括集成电路的有源电路部件的有源电路部分位于金属框架的正下方。

公开(公告)号：US20060186545A1

公开(公告)日：2006-08-24

申请号：US11379572

申请日：2006-04-21

Applicant: Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

Inventor： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/53228 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘与顶部互连金属层之间的第一通孔塞。 半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

公开(公告)号：US20060065976A1

公开(公告)日：2006-03-30

申请号：US10711536

申请日：2004-09-24

Applicant: Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

Inventor： Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

IPC: H01L23/48

CPC classification number: H01L24/97 ,  H01L23/15 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Abstract translation: 本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。 在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。 晶片通过其上的凸块或焊盘与玻璃基板连接。 在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。 之后，进行分割步骤，并获得多个芯片级封装结构。

公开(公告)号：US20050202221A1

公开(公告)日：2005-09-15

申请号：US10907959

申请日：2005-04-22

Applicant: Kun-Chih Wang ,  Bing-Chang Wu

Inventor： Kun-Chih Wang ,  Bing-Chang Wu

IPC: H01L23/485 ,  B32B3/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10T428/24917 ,  Y10T428/265 ,  H01L2924/00014

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

Abstract translation: 强化焊盘结构包括限定在应力缓冲电介质层上的可粘合金属层和在应力缓冲介质层下设置的第一金属间电介质（IMD）层中的中间金属层。 中间金属层位于可接合的金属层的正下方，并且与可结合金属层电连接，多个通孔与可结合的金属层集成。 在第一IMD层下面的第二IMD层中金属框架被镶嵌。 金属框架直接位于中间金属层的正下方，用于抵抗在接合期间施加在可接合金属层上的机械应力，当所述应力缓冲介电层的厚度大于2000埃时，可以省略镶嵌的金属框架。 包括集成电路的有源电路部件的有源电路部分位于金属框架的正下方。

公开(公告)号：US06348398B1

公开(公告)日：2002-02-19

申请号：US09849131

申请日：2001-05-04

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: H01L2182

CPC classification number: H01L24/03 ,  H01L21/76802 ,  H01L23/5256 ,  H01L24/02 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/00014

Abstract: A method of forming pad openings and fuse openings over a wafer. A wafer having pads and fuses thereon is provided. A passivation layer and a photoresist layer are sequentially formed over the wafer. A photo-exposure and development operation is conducted to remove the photoresist layer above the pads. An etching operation is conducted to remove the passivation layer above the pads as well as the photoresist layer and a portion of the passivation layer above the fuses. Finally, the photoresist layer is removed.

Abstract translation: 在晶片上形成焊盘开口和熔断器开口的方法。 提供其上具有焊盘和保险丝的晶片。 在晶片上依次形成钝化层和光致抗蚀剂层。 进行曝光和显影操作以去除衬垫上方的光致抗蚀剂层。 进行蚀刻操作以去除焊盘上方的钝化层以及保护层上方的光致抗蚀剂层和钝化层的一部分。 最后，去除光致抗蚀剂层。

公开(公告)号：US06080646A

公开(公告)日：2000-06-27

申请号：US81423

申请日：1998-05-20

Applicant: Kun-Chih Wang

Inventor： Kun-Chih Wang

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/495

Abstract: A method of fabricating a MOS transistor having an aluminum gate is disclosed. On a MOS transistor having a polysilicon gate, an insulating layer is first formed. The device surface is then polished by CMP to expose the polysilicon gate. Then, an aluminum layer is formed on the substrate and then processed through annealing at more than 500.degree. C. so that a portion of the aluminum layer substitutes the polysilicon gate to form an aluminum gate. After removing the substituted polysilicon and the non-reacted aluminum, the NMOS transistor with an aluminum gate is completed.

Abstract translation: 公开了一种制造具有铝栅极的MOS晶体管的方法。 在具有多晶硅栅极的MOS晶体管上，首先形成绝缘层。 然后通过CMP抛光器件表面以暴露多晶硅栅极。 然后，在基板上形成铝层，然后通过在500℃以上的退火进行处理，使得铝层的一部分代替多晶硅栅极形成铝栅极。 在去除取代的多晶硅和未反应的铝之后，完成具有铝栅极的NMOS晶体管。