公开(公告)号：US6150259A

公开(公告)日：2000-11-21

申请号：US191162

申请日：1998-11-13

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76856

Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Abstract translation: 提供一种用于形成金属插头的方法。 该方法用于当胶/阻隔层已经形成一段时间时，在沟槽内的胶/阻挡层上形成没有孔的金属塞。 提供其中具有沟槽的衬底和与衬底的轮廓保形的形成的胶/阻挡层。 在胶/阻隔层上进行后处理以防止吸湿并使胶/屏障变得致密。 后处理包括等离子体处理或深UV加激光处理。 在执行后处理步骤之后，至少在胶/阻挡层上形成金属层以填充沟槽。 去除填充沟槽以外的金属层以形成金属塞。

公开(公告)号：US6013581A

公开(公告)日：2000-01-11

申请号：US166821

申请日：1998-10-05

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21/768 ,  H05K3/00 ,  H05K3/38 ,  H05K3/46 ,  H01B13/00

CPC classification number: H01L21/76826 ,  H01L21/76813 ,  H01L21/76831 ,  H05K3/465 ,  H05K2203/0384 ,  H05K2203/095 ,  H05K3/002 ,  H05K3/388

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract translation: 一种用于防止在双镶嵌工艺中发生中毒的沟槽和通孔的方法，该方法包括在开口充满导电材料之前，在开口周围的暴露介电层的表面上进行致密化处理，例如等离子体处理。 电介质层的致密表面能够有效地防止由脱气现象引起的中毒的沟槽和通孔的发生。

公开(公告)号：US5883004A

公开(公告)日：1999-03-16

申请号：US920172

申请日：1997-08-25

Applicant: Hao-Kuang Shiu ,  Kun-Lin Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Hao-Kuang Shiu ,  Kun-Lin Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31053 ,  H01L21/76819

Abstract: A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.

Abstract translation: 公开了一种平面化层间电介质的方法。 本发明包括首先在半导体衬底上形成阻挡层。 接下来，通过旋涂玻璃技术在阻挡层上形成缓冲层。 在缓冲层上形成电介质层，其中介电层的蚀刻速率大于缓冲层的蚀刻速率，势垒层用作来自电介质层的自掺杂块。 最后，使用缓冲层作为缓冲层来回蚀介电层，从而平坦化介电层。