公开(公告)号：US06492240B1

公开(公告)日：2002-12-10

申请号：US09661701

申请日：2000-09-14

Applicant: Shyan-Yhu Wang ,  Kun-Lin Wu

Inventor： Shyan-Yhu Wang ,  Kun-Lin Wu

IPC: H01L2120

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.

Abstract translation: 通过在用于ADSL（非对称数字用户线）宽带服务应用的混合信号集成电路中处理多晶硅层的表面，改善了作为多晶硅的高电阻电阻的性能。 在形成电阻器之后，当执行退火步骤时，多晶硅层的该被处理表面将防止电阻器中的离子向外扩散。

公开(公告)号：US06190995B1

公开(公告)日：2001-02-20

申请号：US09208282

申请日：1998-12-08

Applicant: Kun-Lin Wu ,  Cheng-Jung Hsu

Inventor： Kun-Lin Wu ,  Cheng-Jung Hsu

IPC: H01L2176

CPC classification number: H01L21/76224

Abstract: A method of fabricating shallow trench isolation. A silicon oxide layer is formed on a substrate. The silicon oxide layer is patterned and a portion of the substrate is removed to form a trench within the substrate. A liner oxide layer is formed on the sidewall of the trench. An insulating layer is formed on the substrate and filled in the trench. A portion of the insulating layer is removed by CMP to expose the silicon oxide layer. The silicon oxide layer is removed and the STI structure is completed.

Abstract translation: 一种制造浅沟槽隔离的方法。 在基板上形成氧化硅层。 对氧化硅层进行构图，并且去除衬底的一部分以在衬底内形成沟槽。 衬垫氧化物层形成在沟槽的侧壁上。 在衬底上形成绝缘层并填充在沟槽中。 通过CMP去除绝缘层的一部分以暴露氧化硅层。 去除氧化硅层并完成STI结构。

公开(公告)号：US6120366A

公开(公告)日：2000-09-19

申请号：US225367

申请日：1999-01-04

Applicant: Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Edward Yang ,  Kun-Lin Wu ,  Fu-Yang Yu

Inventor： Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Edward Yang ,  Kun-Lin Wu ,  Fu-Yang Yu

IPC: B24B37/26 ,  B24D13/12 ,  B24D13/14 ,  H01L21/304 ,  B23F21/03 ,  B24B1/00

CPC classification number: B24B37/26

Abstract: The invention provides a chemical-mechanical polishing pad, which includes a plurality of annular grooves and a plurality of streamline grooves designed according to principles of the hydrodynamics. The streamline grooves of polishing pad are designed according to flow equations derived from source flow and vortex flow, and the streamline grooves of polishing pad uniformly distribute the slurry on the polishing pad. An angle and a depth of the streamline groove, which are calculated by boundary layer effect of the streamline groove function, are used to design an optimum structure for polishing pad.

Abstract translation: 本发明提供了一种化学机械抛光垫，其包括多个环形槽和根据流体动力学原理设计的多条流线槽。 抛光垫的流线槽根据源流和涡流的流动方程设计，抛光垫的流线槽将浆料均匀分布在抛光垫上。 使用由流线槽功能的边界层效应计算的流线槽的角度和深度来设计抛光垫的最佳结构。

公开(公告)号：US6071806A

公开(公告)日：2000-06-06

申请号：US152921

申请日：1998-09-14

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76825 ,  H01L21/31058 ,  H01L21/76813 ,  H01L21/76831

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an electron-beam process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract translation: 一种用于防止在双镶嵌工艺中发生中毒的沟槽和通孔的方法，该方法包括在开口之前的开口周围的暴露介电层的表面上进行诸如电子束工艺的致密化处理，该导电材料填充有导电材料 。 电介质层的致密表面能够有效地防止由脱气现象引起的中毒的沟槽和通孔的发生。

公开(公告)号：US08389410B2

公开(公告)日：2013-03-05

申请号：US13087356

申请日：2011-04-14

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/302

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Abstract translation: 化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅酸氢钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US07947603B2

公开(公告)日：2011-05-24

申请号：US11965757

申请日：2007-12-28

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/302

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Abstract translation: 用于形成导电互连的化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH 4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US6119294A

公开(公告)日：2000-09-19

申请号：US232203

申请日：1999-01-14

Applicant: Chien-Hsin Lai ,  Juen-Kuen Lin ,  Kun-Lin Wu ,  Peng-Yih Peng

Inventor： Chien-Hsin Lai ,  Juen-Kuen Lin ,  Kun-Lin Wu ,  Peng-Yih Peng

IPC: H01L21/00 ,  A46B13/02

CPC classification number: H01L21/67046 ,  H01L21/6704

Abstract: An auto brush pressure cleaning system is described. The system includes a first pneumatic brush, a second pneumatic brush disposed to align with the first pneumatic brush adjacent and parallel to the first pneumatic brush, and a computer. The system also includes a first brush pressure regulator electrically coupled to the computer and transmitting a first and a second signal to the computer and a second brush pressure regulator coupled to the second pneumatic brush and the first brush pressure regulator through a first three-way valve and electrically coupled to the computer, wherein the second pneumatic brush transmits a third signal to the second brush pressure regulator and to the first brush pressure regulator and the second brush pressure regulator transmits a fourth signal to the computer. The system further includes a first electro-pressure regulator coupled to the first brush pressure regulator and the first pneumatic brush through a second three-way valve, wherein the first brush pressure regulator receives a fifth signal from the first pneumatic brush and a second electro-pressure regulator coupled to the second pneumatic brush and electrically coupled to the first electro-pressure regulator and the computer, wherein the computer transmits a sixth signal to the second and the first electro-pressure regulators.

Abstract translation: 描述了一种自动刷式压力清洗系统。 该系统包括第一气动刷，设置成与第一气动刷相邻并平行于第一气动刷的第二气动刷以及计算机。 该系统还包括电耦合到计算机并将第一和第二信号传送到计算机的第一电刷压力调节器和通过第一三通阀耦合到第二气动刷和第一电刷压力调节器的第二电刷压力调节器 并且电耦合到所述计算机，其中所述第二气动刷将第三信号传输到所述第二电刷压力调节器和所述第一电刷压力调节器，并且所述第二电刷压力调节器将第四信号传输到所述计算机。 该系统还包括通过第二三通阀联接到第一电刷压力调节器和第一气动刷的第一电压调节器，其中第一电刷压力调节器接收来自第一气动刷的第五信号和第二电 - 耦合到第二气动刷并且电耦合到第一电压调节器和计算机的压力调节器，其中计算机向第二和第一电压调节器传输第六信号。

公开(公告)号：US6057248A

公开(公告)日：2000-05-02

申请号：US897282

申请日：1997-07-21

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21/306 ,  H01L21/4763

CPC classification number: H01L21/02065

Abstract: A method of removing residual contaminants in grooves of an alignment mark of a semiconductor wafer after a chemical-mechanical polishing is disclosed. The method includes scrubbing the semiconductor wafer using conventional scrubbing technique. Next, the semiconductor wafer is etched back to remove a damaged layer, which is formed during the chemical-mechanical polishing, over the semiconductor wafer. Finally, the semiconductor wafer is cleaned, for example, by NH.sub.4 OH/H.sub.2 O.sub.2 /DI, agitated by a megasonic source, thereby substantially removing the residual contaminants from the alignment mark.

Abstract translation: 公开了一种在化学机械抛光之后去除半导体晶片的对准标记的凹槽中残留污染物的方法。 该方法包括使用常规洗涤技术擦洗半导体晶片。 接下来，将半导体晶片回蚀刻以除去在化学机械抛光期间形成的受损层在半导体晶片上。 最后，例如通过NH 4 OH / H 2 O 2 / DI清洗半导体晶片，用兆声波源进行搅拌，从而基本上从对准标记中除去残留的污染物。

公开(公告)号：US06234876B1

公开(公告)日：2001-05-22

申请号：US09425454

申请日：1999-10-22

Applicant: Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

Inventor： Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

IPC: B24B100

CPC classification number: B24B37/32 ,  B24B37/042 ,  B24B57/02

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

公开(公告)号：US06197650B1

公开(公告)日：2001-03-06

申请号：US09314630

申请日：1999-05-15

Applicant: Kun-Lin Wu

Inventor： Kun-Lin Wu

IPC: H01L2120

CPC classification number: H01L28/55 ,  H01L21/76838

Abstract: A method for forming capacitor is proposed. The key point of the invention is that bottom plate and dielectric layer of capacitor are formed before metal interconnect is formed. Thus, thermal treatment of dielectric layer does not affect metal interconnect. Therefore, conventional fault that quality of dielectric layer is degraded by scant annealing is avoided, and then dielectric layer and metal interconnect can be optimized respectively. Obviously, the ultimate advantage of the proposed method is that not only breakdown voltage of dielectric layer is increased by annealing but also quality of metal interconnect is not affected by annealing. Therefore, an incidental advantage of the proposed method is that the method is beneficial to form both capacitor and metal interconnect.

Abstract translation: 提出了一种形成电容器的方法。 本发明的关键在于在形成金属互连之前形成电容器的底板和电介质层。 因此，电介质层的热处理不影响金属互连。 因此，避免了通过不均匀退火导致介质层质量下降的常规故障，然后可以分别优化介质层和金属互连。 显然，所提出的方法的最终优点是不仅通过退火而增加介电层的击穿电压，而且金属互连的质量也不受退火的影响。 因此，所提出的方法的附带优点是该方法有利于形成电容器和金属互连。