公开(公告)号：US20070126943A1

公开(公告)日：2007-06-07

申请号：US11295422

申请日：2005-12-05

申请人： Mu-Chia Lee ,  Chun-Wei Huang ,  Hung-Che Lu ,  Kuo-Hung Kuo ,  Hong-Bin Li ,  Wen-Kuei Lai ,  Chia-Yi Tsai ,  Yu-Chi Chang ,  Hau-Chiun Li ,  Wei-Chih Chang

发明人： Mu-Chia Lee ,  Chun-Wei Huang ,  Hung-Che Lu ,  Kuo-Hung Kuo ,  Hong-Bin Li ,  Wen-Kuei Lai ,  Chia-Yi Tsai ,  Yu-Chi Chang ,  Hau-Chiun Li ,  Wei-Chih Chang

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  G02F2201/18

摘要： The invention discloses a stacked storage capacitor structure for a LTPS TFT-LCD comprising a processed substrate, a first storage capacitor and a second storage capacitor. The first storage capacitor comprises a first conductive layer, a second conductive layer and a first insulating layer therebetween. The stacked storage capacitor structure further comprises a third conductive layer including a first portion and an extended second portion. The second storage capacitor comprises the second conductive layer, the extended second portion of the third conductive layer and a second insulating layer therebetween.

摘要翻译： 本发明公开了一种包括处理衬底，第一存储电容器和第二存储电容器的LTPS TFT-LCD的堆叠存储电容器结构。 第一存储电容器包括第一导电层，第二导电层和第一绝缘层。 层叠的存储电容器结构还包括第三导电层，其包括第一部分和延伸的第二部分。 第二存储电容器包括第二导电层，第三导电层的延伸的第二部分和其间的第二绝缘层。

公开(公告)号：US07209191B2

公开(公告)日：2007-04-24

申请号：US10462496

申请日：2003-06-16

申请人： Wei-Chih Chang

发明人： Wei-Chih Chang

IPC分类号： G02F1/1343 ,  G02F1/1335

CPC分类号： G02F1/136213 ,  G02F1/133555

摘要： A liquid crystal display is provided. The liquid crystal display includes a common electrode, a liquid crystal layer, a data line, a transmissive electrode, a reflective electrode, an auxiliary electrode and a dielectric layer. The transmissive electrode is electrically connected to the data line and defines a first capacitor device along with the liquid crystal layer and the common electrode. The reflective electrode defines a second capacitor device along with the liquid crystal layer and the common electrode. The auxiliary electrode is electrically connected to the transmissive electrode. The dielectric layer is disposed between the auxiliary electrode and the reflective electrode and defines a third capacitor device along with the auxiliary electrode and the reflective electrode. The third capacitor device is electrically connected to the second capacitor device in series.

摘要翻译： 提供液晶显示器。 液晶显示器包括公共电极，液晶层，数据线，透射电极，反射电极，辅助电极和电介质层。 透射电极与数据线电连接，并与液晶层和公共电极一起形成第一电容器器件。 反射电极与液晶层和公共电极一起形成第二电容器装置。 辅助电极与透射电极电连接。 电介质层设置在辅助电极和反射电极之间，并且与辅助电极和反射电极一起限定第三电容器装置。 第三电容器装置串联地电连接到第二电容器装置。

公开(公告)号：US06873390B2

公开(公告)日：2005-03-29

申请号：US10438660

申请日：2003-05-14

申请人： Wei-Chih Chang ,  Fu-Jen Ko

发明人： Wei-Chih Chang ,  Fu-Jen Ko

IPC分类号： G02F1/1335 ,  G02F1/1339

CPC分类号： G02F1/133553 ,  G02F1/133514 ,  G02F1/1339

摘要： A reflective liquid crystal display apparatus. The reflective liquid crystal display apparatus includes a substrate having a first region and a second region; a reflective layer disposed on the substrate in the first region; a photo spacer disposed on the substrate in the second region; a conductive layer disposed on the photoresist spacer; a liquid crystal layer interposed among the reflective layer, the photoresist spacer, and the conductive layer; a color filter layer disposed on the conductive layer; a compensation layer disposed on the color filter layer; and a polarization plate disposed on the compensation layer.

摘要翻译： 反射型液晶显示装置。 反射型液晶显示装置包括：具有第一区域和第二区域的基板; 设置在所述第一区域中的所述基板上的反射层; 设置在所述第二区域中的所述基板上的照片间隔件; 设置在光致抗蚀剂间隔物上的导电层; 插入在反射层，光致抗蚀剂间隔物和导电层之间的液晶层; 布置在所述导电层上的滤色器层; 设置在滤色器层上的补偿层; 以及设置在所述补偿层上的偏振板。

公开(公告)号：US08954628B2

公开(公告)日：2015-02-10

申请号：US13489027

申请日：2012-06-05

申请人： Ching-Chung Hung ,  Yu-Peng Lai ,  Wei-Chih Chang

发明人： Ching-Chung Hung ,  Yu-Peng Lai ,  Wei-Chih Chang

IPC分类号： G06F3/00 ,  G06F13/12

CPC分类号： G06F1/1632 ,  G06F13/4022 ,  G06F13/4081 ,  Y02D10/14 ,  Y02D10/151

摘要： An electronic device includes a housing, a connector port and a switching device. The connector port receives a peripheral device. The processor is electrically connected to the connector port and includes a detection pin and a 1-wire pin. The switching device is coupled between the connector port and the processor to selectively connect the connector port to one of the detection pin or the 1-wire pin. When the peripheral device is inserted into the connector port, the processor controls the switching device to connect the connector port to the detection pin to determine whether the connected peripheral device is a 1-wire device. When the processor determines that the connected peripheral device is a 1-wire device, the processor controls the switching device to connect the connector port to the 1-wire pin and the processor executes 1-wire communication with the peripheral device via the 1-wire pin.

摘要翻译： 电子设备包括壳体，连接器端口和开关装置。 连接器端口接收外围设备。 处理器电连接到连接器端口，并包括检测引脚和1线引脚。 开关装置耦合在连接器端口和处理器之间，以将连接器端口选择性地连接到检测销或1线引脚之一。 当外围设备插入连接器端口时，处理器控制切换设备将连接器端口连接到检测引脚，以确定连接的外围设备是否为1线设备。 当处理器确定连接的外围设备是1线设备时，处理器控制开关设备将连接器端口连接到1线引脚，处理器通过1线制与外围设备执行1线通信 销。

公开(公告)号：US20130322010A1

公开(公告)日：2013-12-05

申请号：US13489027

申请日：2012-06-05

申请人： Ching-Chung Hung ,  Yu-Peng Lai ,  Wei-Chih Chang

发明人： Ching-Chung Hung ,  Yu-Peng Lai ,  Wei-Chih Chang

IPC分类号： G06F1/16

CPC分类号： G06F1/1632 ,  G06F13/4022 ,  G06F13/4081 ,  Y02D10/14 ,  Y02D10/151

摘要： An electronic device includes a housing, a connector port and a switching device. The connector port receives a peripheral device. The processor is electrically connected to the connector port and includes a detection pin and a 1-wire pin. The switching device is coupled between the connector port and the processor to selectively connect the connector port to one of the detection pin or the 1-wire pin. When the peripheral device is inserted into the connector port, the processor controls the switching device to connect the connector port to the detection pin to determine whether the connected peripheral device is a 1-wire device. When the processor determines that the connected peripheral device is a 1-wire device, the processor controls the switching device to connect the connector port to the 1-wire pin and the processor executes 1-wire communication with the peripheral device via the 1-wire pin.

摘要翻译： 电子装置包括壳体，连接器端口和开关装置。 连接器端口接收外围设备。 处理器电连接到连接器端口，并包括检测引脚和1线引脚。 开关装置耦合在连接器端口和处理器之间，以将连接器端口选择性地连接到检测销或1线引脚之一。 当外围设备插入连接器端口时，处理器控制切换设备将连接器端口连接到检测引脚，以确定连接的外围设备是否为1线设备。 当处理器确定连接的外围设备是1线设备时，处理器控制开关设备将连接器端口连接到1线引脚，处理器通过1线制与外围设备执行1线通信 销。

公开(公告)号：US20130207594A1

公开(公告)日：2013-08-15

申请号：US13397203

申请日：2012-02-15

申请人： Ching-Chung HUNG ,  Yu-Peng Lai ,  Wei-Chih Chang

发明人： Ching-Chung HUNG ,  Yu-Peng Lai ,  Wei-Chih Chang

IPC分类号： H02J7/00

CPC分类号： H01M10/44 ,  H02J7/007 ,  H02J2007/0062

摘要： A portable electronic device is provided. Connector includes the first and data pins. Processor includes input and output pins and detection pin coupled to the input pin. First resistor is coupled between the detection pin and first voltage. When the processor detects that the first and second pins of charger are coupled to the first and second data pins of the connector, the processor provides switching signal to the selector, so as to couple the first and second data pins of the connector to the input and output pins of the processor, respectively, and to provide second voltage different from the first voltage, to the second pin of the charger via the output pin. The processor obtains charging current value of the charger according to voltage of the detection pin. The charger includes second resistor coupled between the first and second pins.

摘要翻译： 提供便携式电子设备。 连接器包括第一个和数据引脚。 处理器包括输入和输出引脚以及耦合到输入引脚的检测引脚。 第一个电阻耦合在检测引脚和第一个电压之间。 当处理器检测到充电器的第一和第二引脚耦合到连接器的第一和第二数据引脚时，处理器向切换器提供切换信号，以将连接器的第一和第二数据引脚耦合到输入端 和处理器的输出引脚，并且通过输出引脚将不同于第一电压的第二电压提供给充电器的第二引脚。 处理器根据检测针的电压来获得充电器的充电电流值。 充电器包括耦合在第一和第二引脚之间的第二电阻器。

公开(公告)号：US08312654B2

公开(公告)日：2012-11-20

申请号：US13206616

申请日：2011-08-10

申请人： Wei-Yu Chang ,  Wei-Chih Chang

发明人： Wei-Yu Chang ,  Wei-Chih Chang

IPC分类号： G09F3/20

CPC分类号： G09F3/207 ,  A44B15/005 ,  G09F3/14

摘要： A key tag includes: a body having a recess and a through hole near its one end, a tag sheet accommodated in the recess, and a cover sheet adaptively engaged with the body so as to confine the tag sheet within the recess.

摘要翻译： 钥匙标签包括：具有凹部和靠近其一端的通孔的本体，容纳在凹部中的标签片，以及与本体自适应地接合以将标签片限制在凹部内的盖片。

公开(公告)号：US20110241752A1

公开(公告)日：2011-10-06

申请号：US13067598

申请日：2011-06-13

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC分类号： H03K5/08

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

摘要翻译： 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

公开(公告)号：US20100163299A1

公开(公告)日：2010-07-01

申请号：US12639150

申请日：2009-12-16

申请人： Hsu-Kuan Hsu ,  Ching-Jung Tsai ,  Shih-Nien Huang ,  Wei-Chih Chang

发明人： Hsu-Kuan Hsu ,  Ching-Jung Tsai ,  Shih-Nien Huang ,  Wei-Chih Chang

IPC分类号： H05K9/00

CPC分类号： H05K1/0253 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/0969

摘要： An electronic device and a high frequency circuit board thereof are disclosed. The high frequency circuit board includes a first dielectric layer, a first signal line formed on the first dielectric layer, a second dielectric layer overlaying the first dielectric layer and covering the first signal line, and a first EMI shielding layer overlaying the second dielectric layer. The first EMI shielding layer has a gap formed thereon. The gap is formed at a position corresponding to the position of the first signal line.

摘要翻译： 公开了一种电子设备及其高频电路板。 高频电路板包括第一电介质层，形成在第一电介质层上的第一信号线，覆盖第一介电层并覆盖第一信号线的第二电介质层和覆盖第二电介质层的第一EMI屏蔽层。 第一EMI屏蔽层在其上形成间隙。 间隙形成在与第一信号线的位置相对应的位置处。

公开(公告)号：US20100097117A1

公开(公告)日：2010-04-22

申请号：US12289132

申请日：2008-10-21

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC分类号： H03L5/00

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

摘要： A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.

摘要翻译： 混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。 输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。 输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管 堆叠的下拉式N型晶体管耦合到I / O焊盘。 栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。 浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压 跟踪电路，以防止漏电流。