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40 条记录 (耗时 0.028 秒)

    RECONFIGURABLE INTERPOLATION FILTER AND ASSOCIATED INTERPOLATION FILTERING METHOD
    32.
    发明申请
    RECONFIGURABLE INTERPOLATION FILTER AND ASSOCIATED INTERPOLATION FILTERING METHOD 审中-公开

    公开(公告)号：US20170244981A1

    公开(公告)日：2017-08-24

    申请号：US15439947

    申请日：2017-02-23

    申请人： MEDIATEK INC.

    发明人： Chi-Hung Chen ,  Yung-Chang Chang ,  Chih-Ming Wang

    IPC分类号： H04N19/82 ,  H04N19/176 ,  H04N19/59 ,  H04N19/182

    CPC分类号： H04N19/82 ,  H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/523 ,  H04N19/59

    摘要： A reconfigurable interpolation filter has an L×1 parallelism integer pixel and sub-integer pixel processing filter and a filter configuration circuit. The L×1 parallelism integer pixel and sub-integer pixel processing filter calculates L filtered samples at a same pixel line in a parallel fashion, wherein L is a positive integer not smaller than one. The filter configuration circuit reconfigures the L×1 parallelism integer pixel and sub-integer pixel processing filter into an (L/M)×M parallelism integer pixel and sub-integer pixel processing filter according to a width of a prediction block. The (L/M)×M parallelism integer pixel and sub-integer pixel processing filter processes the prediction block by calculating L/M filtered samples at each of M pixel lines in a parallel fashion, wherein M is a positive integer not smaller than one, and L/M is a positive integer.

    Data compression method and decompression method
    33.
    发明授权
    Data compression method and decompression method 有权

    公开(公告)号：US09648144B2

    公开(公告)日：2017-05-09

    申请号：US14546213

    申请日：2014-11-18

    申请人： MediaTek Inc.

    发明人： Chi-Cheng Ju ,  Chia-Yun Cheng ,  Yung-Chang Chang ,  Chih-Ming Wang

    IPC分类号： H04L29/06 ,  H03M7/30

    CPC分类号： H04L69/04 ,  H03M7/3059 ,  H04L69/22

    摘要： A transmitter device includes a processing unit and a compression unit. The processing unit obtains a branch of data and partitions the branch of data into a plurality of snippets. Each snippet includes a group of data. The compression unit compresses each snippet into a plurality of packets according to value of each datum included in the corresponding snippet. The compression unit compares the value of each datum with a first threshold value to generate a first packet. The first packet includes first information indicating which data included in the corresponding snippet has the corresponding value not equal to the first threshold value. The compression unit further generates the remaining packets according to the first information.

    METHOD AND SYSTEM WITH DATA REUSE IN INTER-FRAME LEVEL PARALLEL DECODING
    34.
    发明申请
    METHOD AND SYSTEM WITH DATA REUSE IN INTER-FRAME LEVEL PARALLEL DECODING 审中-公开
    在帧间并行解码中具有数据重用的方法和系统

    公开(公告)号：US20160191935A1

    公开(公告)日：2016-06-30

    申请号：US14979578

    申请日：2015-12-28

    申请人： MEDIATEK INC.

    发明人： Ping Chao ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang

    IPC分类号： H04N19/423 ,  G06F5/06 ,  H04N19/44 ,  G06F12/08

    CPC分类号： H04N19/423 ,  G06F5/065 ,  G06F12/0811 ,  G06F2205/067 ,  G06F2212/283 ,  H04N19/127 ,  H04N19/172 ,  H04N19/436 ,  H04N19/44

    摘要： A multi-core decoder system and an associated method use a decoding progress synchronizer to reduce bandwidth consumption for decoding a video bitstream is disclosed. In one embodiment of the present invention, the multi-core decoder system includes a shared reference data buffer coupled to the multiple decoder cores and an external memory. The shared reference data buffer stores reference data received from the external memory and provides the reference data the multiple decoder cores for decoding video data. The multi-core decoder system also includes one or more decoding progress synchronizers coupled to the multiple decoder cores to detect decoding-progress information associated with the multiple decoder cores or status information of the shared reference data buffer, and to control decoding progress for the multiple decoder cores.

    摘要翻译： 公开了一种多核解码器系统和相关联的方法，使用解码进步同步器来减少用于解码视频比特流的带宽消耗。 在本发明的一个实施例中，多核解码器系统包括耦合到多个解码器核心的共享参考数据缓冲器和外部存储器。 共享参考数据缓冲器存储从外部存储器接收的参考数据，并为参考数据提供用于解码视频数据的多个解码器核心。 多核解码器系统还包括耦合到多个解码器核心的一个或多个解码进步同步器，以检测与多个解码器核心相关联的解码进度信息或共享参考数据缓冲器的状态信息，并且控制多个解码器的解码进程 解码器核心。

    THERMAL MANAGEMENT METHOD AND ELECTRONIC SYSTEM WITH THERMAL MANAGEMENT MECHANISM
    36.
    发明申请
    THERMAL MANAGEMENT METHOD AND ELECTRONIC SYSTEM WITH THERMAL MANAGEMENT MECHANISM 审中-公开
    热管理方法和电子系统与热管理机制

    公开(公告)号：US20160179150A1

    公开(公告)日：2016-06-23

    申请号：US14908116

    申请日：2015-06-12

    申请人： MEDIATEK INC.

    发明人： Tsu-Ming Liu ,  Tsui-Shan Chang ,  Chi-Cheng Ju ,  Chih-Ming Wang

    IPC分类号： G06F1/20 ,  G05B15/02

    CPC分类号： G06F1/206 ,  G05B15/02 ,  G05D23/1917 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  H04N5/23216 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D10/24

    摘要： Disclosed is an electronic system with a thermal control mechanism, comprising: an image/video processing module (101), configured to process at least one image or video data; a parameter acquiring device (103), configured to acquire at least one device parameter corresponding to a first device of the image/video processing module (101); and a thermal management device (105), configured to adjust at least one operating parameter for a second device of the image/video processing module (101) according to the device parameter to control a temperature of the image/video processing module (101).

    摘要翻译： 公开了一种具有热控制机构的电子系统，包括：图像/视频处理模块（101），被配置为处理至少一个图像或视频数据; 参数获取装置，被配置为获取与所述图像/视频处理模块（101）的第一装置相对应的至少一个装置参数; 以及热管理装置（105），被配置为根据所述设备参数调整所述图像/视频处理模块（101）的第二设备的至少一个操作参数，以控制所述图像/视频处理模块（101）的温度， 。

    DECODING APPARATUS CAPABLE OF CONTROLLING REPETITION NUMBER OF SCAN PROCEDURE BASED ON AT LEAST ONE SYNTAX ELEMENT DECODING RESULT AND RELATED METHOD
    40.
    发明申请
    DECODING APPARATUS CAPABLE OF CONTROLLING REPETITION NUMBER OF SCAN PROCEDURE BASED ON AT LEAST ONE SYNTAX ELEMENT DECODING RESULT AND RELATED METHOD 有权
    基于至少一个语音元素解码结果和相关方法的解码设备可以控制重复次数的扫描程序

    公开(公告)号：US20160021378A1

    公开(公告)日：2016-01-21

    申请号：US14767912

    申请日：2015-01-21

    申请人： MEDIATEK INC.

    发明人： Chia-Yun Cheng ,  Chi-Cheng Ju ,  Yung-Chang Chang ,  Chih-Ming Wang

    IPC分类号： H04N19/176 ,  H04N19/44 ,  H04N19/60

    CPC分类号： H04N19/91 ,  H04N19/129 ,  H04N19/176 ,  H04N19/18 ,  H04N19/44 ,  H04N19/463 ,  H04N19/60 ,  H04N19/70 ,  H04N19/82

    摘要： A decoding apparatus has an arithmetic decoder and a controller. A counter logic of the controller generates a first statistics result according to a first syntax element decoding result. A control logic of the controller instructs the arithmetic decoder to perform a first scan procedure at least once to generate the first syntax element decoding result of transform coefficients of a transform coefficient block, controls a repetition number of a second scan procedure based at least partly on the first statistics result, and instructs the arithmetic decoder to perform the second scan procedure at least once to generate a second syntax element decoding result of the transform coefficients. The first scan procedure decodes a first coded syntax element of one transform coefficient when performed by the arithmetic decoder once. The second scan procedure decodes a second coded syntax element of one transform coefficient when performed by the arithmetic decoder once.

    摘要翻译： 解码装置具有算术解码器和控制器。 控制器的计数器逻辑根据第一语法元素解码结果产生第一统计结果。 控制器的控制逻辑指示算术解码器至少执行一次第一扫描过程以产生变换系数块的变换系数的第一语法元素解码结果，至少部分地基于第二扫描过程控制重复次数 第一统计结果，并且指示算术解码器至少执行第二扫描过程以产生变换系数的第二语法元素解码结果。 当由算术解码器执行一次时，第一扫描程序解码一个变换系数的第一编码语法元素。 当由算术解码器执行一次时，第二扫描程序解码一个变换系数的第二编码语法元素。