公开(公告)号：US20170278832A1

公开(公告)日：2017-09-28

申请号：US15618210

申请日：2017-06-09

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.

公开(公告)号：US20170141041A1

公开(公告)日：2017-05-18

申请号：US15338652

申请日：2016-10-31

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Nai-Wei LIU ,  I-Hsuan PENG ,  Wei-Che HUANG

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.

公开(公告)号：US20170040266A1

公开(公告)日：2017-02-09

申请号：US15331016

申请日：2016-10-21

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU ,  Wei-Che HUANG ,  Che-Ya CHOU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装，其包括具有第一表面和与第一基板相对的第二表面的第一再分布层（RDL）结构。 第一RDL结构包括靠近第一RDL结构的第一表面的多个第一导电迹线。 天线图案靠近第一RDL结构的第二表面设置。 第一半导体管芯设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构通过第一RDL结构的多个第一导电迹线与天线图案间隔开。

公开(公告)号：US20160343694A1

公开(公告)日：2016-11-24

申请号：US15066241

申请日：2016-03-10

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L21/78 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.

Abstract translation: 提供半导体封装组件。 半导体封装组件包括半导体封装。 半导体封装包括半导体管芯。 再分配层（RDL）结构设置在半导体管芯上并与半导体管芯电连接。 有源或无源元件设置在半导体管芯和RDL结构之间。 模制化合物围绕半导体管芯和有源或无源元件。