公开(公告)号：US20210175137A1

公开(公告)日：2021-06-10

申请号：US17182525

申请日：2021-02-23

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L23/04 ,  H01L25/18 ,  H01L23/16

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

公开(公告)号：US20200075572A1

公开(公告)日：2020-03-05

申请号：US16674298

申请日：2019-11-05

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  I-Hsuan PENG ,  Tzu-Hung LIN

IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

公开(公告)号：US20170243826A1

公开(公告)日：2017-08-24

申请号：US15418896

申请日：2017-01-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Nai-Wei LIU ,  Wei-Che HUANG

IPC: H01L23/538 ,  H01L49/02 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.

公开(公告)号：US20170033079A1

公开(公告)日：2017-02-02

申请号：US15184657

申请日：2016-06-16

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60232 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10156 ,  H01L2224/11 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.

Abstract translation: 提供半导体封装结构。 半导体封装结构包括在基板上的第一电子部件。 半导体封装结构还包括堆叠在第一电子部件上的第二电子部件。 第一电子部件的有源表面面向第二电子部件的有效表面。 半导体封装结构还包括在第一电子元件上并包围第二电子元件的模塑料。 此外，半导体封装结构包括堆叠在第二电子部件和模塑料上的第三电子部件。

公开(公告)号：US20160343695A1

公开(公告)日：2016-11-24

申请号：US15071573

申请日：2016-03-16

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/16 ,  H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/80 ,  H01L24/89 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73259 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/802 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/80001

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

Abstract translation: 提供半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括第一半导体管芯。 第一再分配层（RDL）结构耦合到第一半导体管芯并且包括第一导电迹线。 半导体封装组件还包括结合到第一半导体封装的第二半导体封装。 第二半导体封装包括第二半导体管芯。 第二半导体管芯的有源表面面向第一半导体管芯的有效表面。 第二RDL结构耦合到第二半导体管芯并且包括第二导电迹线。 第一导电迹线与第二导电迹线直接接触。

公开(公告)号：US20230197684A1

公开(公告)日：2023-06-22

申请号：US18170078

申请日：2023-02-16

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Yi-Jou LIN

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/3128 ,  H01L2224/16113 ,  H01L24/16 ,  H01L23/3675 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

公开(公告)号：US20210313299A1

公开(公告)日：2021-10-07

申请号：US17208198

申请日：2021-03-22

Applicant: MEDIATEK INC.

Inventor： Yi-Lin TSAI ,  Wen-Sung HSU ,  I-Hsuan PENG ,  Yi-Jou LIN

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

公开(公告)号：US20160276324A1

公开(公告)日：2016-09-22

申请号：US15014636

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括包括第一半导体管芯的第一半导体封装。 第一再分配层（RDL）结构耦合到第一半导体管芯。 第一再分配层（RDL）结构包括设置在第一层级的第一导电迹线。 第二导电迹线设置在第二层级。 位于第一导电迹线和第二导电迹线之间的第一金属间电介质（IMD）层之外的第一金属间介电层（IMD）层和第二金属间介电层（IMD）层。

公开(公告)号：US20240153887A1

公开(公告)日：2024-05-09

申请号：US18403974

申请日：2024-01-04

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/00 ,  H01L23/043 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/043 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/5385 ,  H01L2224/16227

Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

公开(公告)号：US20190043771A1

公开(公告)日：2019-02-07

申请号：US16002138

申请日：2018-06-07

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU

IPC: H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L23/00

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.