公开(公告)号：US20140095753A1

公开(公告)日：2014-04-03

申请号：US14033470

申请日：2013-09-22

Applicant: Mellanox Technologies Ltd.

Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口​​传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。

公开(公告)号：US20240143539A1

公开(公告)日：2024-05-02

申请号：US17977894

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Richard Graham

IPC: G06F15/173 ,  G06F13/32

CPC classification number: G06F15/17331 ,  G06F13/32

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

公开(公告)号：US20240012773A1

公开(公告)日：2024-01-11

申请号：US17858102

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US10528518B2

公开(公告)日：2020-01-07

申请号：US15681390

申请日：2017-08-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Richard Graham ,  Ana Gainaru

IPC: G06F15/173 ,  H04L12/931 ,  G06F13/12

Abstract: An all-to-all communication operation which is carried out in a fabric of networked entities by defining in each of the entities a plurality of memory regions of contiguous memory addresses holding messages therein, and exchanging the messages repeatedly with all the other entities. Relatively small messages are copied using a CPU and larger messages are transmitted using scatter/gather facilities.

公开(公告)号：US20190149486A1

公开(公告)日：2019-05-16

申请号：US16181376

申请日：2018-11-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

IPC: H04L12/879 ,  H04L12/883 ,  H04L12/861 ,  H04L12/935

Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.

公开(公告)号：US10284383B2

公开(公告)日：2019-05-07

申请号：US15250953

申请日：2016-08-30

Applicant: Mellanox Technologies Ltd.

Inventor： Gil Bloch ,  Diego Crupnicoff ,  Benny Koren ,  Oded Wertheim ,  Lion Levi ,  Richard Graham ,  Michael Kagan

IPC: H04L12/24 ,  H04L12/18 ,  H04L12/44

Abstract: A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements, and child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.

公开(公告)号：US09742855B2

公开(公告)日：2017-08-22

申请号：US14834443

申请日：2015-08-25

Applicant: Mellanox Technologies Ltd.

Inventor： Shahaf Shuler ,  Noam Bloch ,  Ofer Hayut ,  Richard Graham ,  Ariel Shahar ,  Yossef Itigin

IPC: H04L29/08 ,  H04L29/06 ,  H04L12/861

CPC classification number: H04L67/26 ,  H04L49/9068 ,  H04L67/10 ,  H04L67/1093 ,  H04L67/1097 ,  H04L69/06

Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.