公开(公告)号：US20200348883A1

公开(公告)日：2020-11-05

申请号：US16932032

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/02

Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.

公开(公告)号：US10446198B2

公开(公告)日：2019-10-15

申请号：US15977815

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US20190295607A1

公开(公告)日：2019-09-26

申请号：US16439628

申请日：2019-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C5/14 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/10

Abstract: An apparatus is disclosed. The apparatus comprises a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US20190102330A1

公开(公告)日：2019-04-04

申请号：US15977818

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US20190102298A1

公开(公告)日：2019-04-04

申请号：US15977808

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US20190028102A1

公开(公告)日：2019-01-24

申请号：US16013827

申请日：2018-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: H03K19/00 ,  G11C11/4093 ,  H03K19/003 ,  G11C11/4094 ,  G11C29/02 ,  H03K19/0175

Abstract: A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes.

公开(公告)号：US09934831B2

公开(公告)日：2018-04-03

申请号：US14247129

申请日：2014-04-07

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1045 ,  G11C7/109

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US11915788B2

公开(公告)日：2024-02-27

申请号：US17727283

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G11C7/22 ,  G06F13/36 ,  G11C7/10 ,  G06F13/16

CPC classification number: G11C7/22 ,  G06F13/36 ,  G11C7/10 ,  G06F13/1689

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

公开(公告)号：US20230420032A1

公开(公告)日：2023-12-28

申请号：US18312747

申请日：2023-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  John D. Porter

IPC: G11C11/4076 ,  G11C11/4074 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C11/4076 ,  G11C11/4074 ,  G06F3/0673 ,  G06F3/0604 ,  G06F3/0659 ,  G06F13/1689

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

公开(公告)号：US20230144541A1

公开(公告)日：2023-05-11

申请号：US18094799

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G11C11/22 ,  G11C29/04 ,  G06F13/16

CPC classification number: G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G06F13/1668 ,  G11C11/2257 ,  G11C11/2277 ,  G11C29/04

Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.