公开(公告)号：US20210257043A1

公开(公告)日：2021-08-19

申请号：US17308448

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt ,  George Raad ,  Seth Eichmeyer ,  Dean Gans

IPC: G11C29/00 ,  G11C17/16 ,  G11C29/02

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

公开(公告)号：US20210232514A1

公开(公告)日：2021-07-29

申请号：US17167475

申请日：2021-02-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20210011868A1

公开(公告)日：2021-01-14

申请号：US17032152

申请日：2020-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20200252069A1

公开(公告)日：2020-08-06

申请号：US16799668

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: H03K19/0185 ,  G11C29/02 ,  H03K19/00 ,  G06F13/40 ,  G11C7/02 ,  G11C29/50

Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

公开(公告)号：US20190109755A1

公开(公告)日：2019-04-11

申请号：US16216742

申请日：2018-12-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: H04L12/24 ,  H04L12/863 ,  H04L25/03

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

公开(公告)号：US20190087366A1

公开(公告)日：2019-03-21

申请号：US16193286

申请日：2018-11-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean Gans ,  Bruce Schober ,  Moo Sung Chae

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1694 ,  G06F13/4068

Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

公开(公告)号：US10180920B2

公开(公告)日：2019-01-15

申请号：US15963615

申请日：2018-04-26

Applicant: Micron Technology, Inc.

Inventor： Dean Gans ,  Bruce Schober ,  Moo Sung Chae

IPC: G06F13/16 ,  G06F13/40

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

公开(公告)号：US20180167055A1

公开(公告)日：2018-06-14

申请号：US15834892

申请日：2017-12-07

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: H03H11/28 ,  H03H11/54

CPC classification number: H03H11/28 ,  G11C7/10 ,  G11C29/025 ,  G11C29/028 ,  H03H11/54 ,  H03K19/0005

Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

公开(公告)号：US20170351451A1

公开(公告)日：2017-12-07

申请号：US15683540

申请日：2017-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean Gans

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/16 ,  G06F13/368

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1668 ,  G06F13/368 ,  G11C7/1051 ,  G11C2207/2254

Abstract: An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.

公开(公告)号：US20160335204A1

公开(公告)日：2016-11-17

申请号：US14712610

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： Dean Gans ,  Bruce Schober ,  Moo Sung Chae

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/4068

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Abstract translation: 公开了用于存储器的非对称输入/输出接口的装置和方法。 示例性设备可以包括接收机和发射机。 接收机可以被配置为接收具有第一电压摆幅并且具有第一压摆率的第一数据信号。 发射机可以被配置为提供具有第二电压摆幅并具有第二压摆率的第二数据信号，其中第一和第二电压摆幅是不同的，并且其中第一和第二转换速率是不同的。