公开(公告)号：US09529736B2

公开(公告)日：2016-12-27

申请号：US14932503

申请日：2015-11-04

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini ,  Emanuele Confalonieri

IPC: G06F12/14 ,  G06F3/06 ,  G06F12/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/14 ,  G06F13/1668 ,  G06F13/4036 ,  G06F13/4221 ,  G06F2212/1052

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

公开(公告)号：US09059261B2

公开(公告)日：2015-06-16

申请号：US14302160

申请日：2014-06-11

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成，随后可以与第一组横向的第二组平行条纹掩模形成。 例如，可以使用一组掩模来蚀刻介电层，以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后，该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。

公开(公告)号：US20130087849A1

公开(公告)日：2013-04-11

申请号：US13687726

申请日：2012-11-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto M. Meotto ,  Giulio Albini ,  Paolo Tessariol ,  Paola Bacciaglia ,  Marcello Mariani

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/02233 ,  H01L21/28282 ,  H01L21/76224 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/66833 ,  H01L29/792

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.

Abstract translation: 本文公开的主题涉及一种制造半导体集成电路器件的方法，更具体地说，涉及一种制造电荷阱NAND快闪存储器件的方法。