公开(公告)号：US09922686B2

公开(公告)日：2018-03-20

申请号：US15159728

申请日：2016-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Huy T. Vo ,  Dirgha Khatri

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22

Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.

公开(公告)号：US20160085260A1

公开(公告)日：2016-03-24

申请号：US14958650

申请日：2015-12-03

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Yantao Ma

IPC: G06F1/06 ,  G06F1/08

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3275 ,  H03K5/1515 ,  Y02D10/126 ,  Y02D10/14

Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.

Abstract translation: 本文描述了用于提供时钟信号的装置和方法。 示例性装置可以包括时钟发生器电路。 时钟发生器电路可以被配置为在时钟路径中选择性地向多路复用器提供第一和第二中间信号，以在第一模式下工作时提供具有第一频率的输出时钟信号，并且选择性地将第一和第二中间时钟信号提供给 时钟路径中的多路复用器，以在第二模式下操作时提供具有第二频率的输出时钟信号。

公开(公告)号：US20240203482A1

公开(公告)日：2024-06-20

申请号：US18494463

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Charles L. Ingalls ,  Shizhong Mei ,  Luoqi Li

IPC: G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C11/4074

Abstract: A memory device may include multiple memory cells configured to store data. The memory device may also include multiple digit lines that carry data to and from a respective memory cell. The memory device may include multiple sense amplifiers each selectively coupled to respective digit lines and including first and second transistors and first and second gut nodes coupled to the first and second transistors, respectively. Each sense amplifier may amplify a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based on respective charges the digit lines, where a gain of the amplification is based on a negative voltage supplied to the sense amplifier and/or negative digit line write back operations.

公开(公告)号：US11967362B2

公开(公告)日：2024-04-23

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C16/04 ,  G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US20230395130A1

公开(公告)日：2023-12-07

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US20190333554A1

公开(公告)日：2019-10-31

申请号：US16508044

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma ,  Huy T. Vo

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

公开(公告)号：US20180336940A1

公开(公告)日：2018-11-22

申请号：US16037546

申请日：2018-07-17

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma ,  Huy T. Vo

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/20 ,  G11C2207/2254

Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

公开(公告)号：US20180315466A1

公开(公告)日：2018-11-01

申请号：US15583023

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US20180308538A1

公开(公告)日：2018-10-25

申请号：US15957742

申请日：2018-04-19

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Adam S. El-Mansouri

IPC: G11C11/22 ,  G11C7/06 ,  H01L27/11502

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.