公开(公告)号：US12021668B2

公开(公告)日：2024-06-25

申请号：US17562588

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03057 ,  H04L25/4917

Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

公开(公告)号：US11907544B2

公开(公告)日：2024-02-20

申请号：US17460013

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

公开(公告)号：US20230343381A1

公开(公告)日：2023-10-26

申请号：US17660199

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4085

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US11735246B2

公开(公告)日：2023-08-22

申请号：US17454963

申请日：2021-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Atsushi Hatakeyama ,  Hyun Yoo Lee ,  Kang-Yong Kim ,  Akiyoshi Yamamoto

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40615

Abstract: Disclosed herein is an apparatus that includes a plurality of memory banks and a refresh controller configured to perform a refresh operation on one or more of the plurality of memory banks having a first state without performing the refresh operation on one or more of the plurality of memory banks having a second state responsive to a first refresh command, and perform the refresh operation on a selected one of the plurality of memory banks responsive to a second refresh command. The refresh controller is configured to bring the selected one of the plurality of memory banks into the second state when the refresh operation is performed responsive to the second refresh command.

公开(公告)号：US11715508B2

公开(公告)日：2023-08-01

申请号：US17387301

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Suryanarayana B. Tatapudi ,  Huy T. Vo ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/4091 ,  G11C11/4094

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

公开(公告)号：US20220206717A1

公开(公告)日：2022-06-30

申请号：US17562560

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G06F3/06

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20220137881A1

公开(公告)日：2022-05-05

申请号：US17513311

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

公开(公告)号：US20220083254A1

公开(公告)日：2022-03-17

申请号：US17022551

申请日：2020-09-16

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first characteristic and a second memory circuit having a second characteristic. Contact pads of the first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US11081158B2

公开(公告)日：2021-08-03

申请号：US16813334

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Suryanarayana B. Tatapudi ,  Huy T. Vo ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

公开(公告)号：US10529398B1

公开(公告)日：2020-01-07

申请号：US16551981

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C8/18 ,  G11C16/32 ,  G11C16/28 ,  G11C16/08

Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.